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-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.cpp12
-rw-r--r--lib/Target/Sparc/SparcV8Instrs.td11
-rw-r--r--lib/Target/Sparc/SparcV8Instrs_F2.td2
-rw-r--r--lib/Target/Sparc/SparcV8Instrs_F3.td3
-rw-r--r--lib/Target/SparcV8/SparcV8Instrs.td11
-rw-r--r--lib/Target/SparcV8/SparcV8Instrs_F2.td2
-rw-r--r--lib/Target/SparcV8/SparcV8Instrs_F3.td3
-rw-r--r--lib/Target/SparcV8/SparcV8RegisterInfo.cpp12
8 files changed, 40 insertions, 16 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index d6fd83a..7f576f9 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -17,8 +17,8 @@
using namespace llvm;
SparcV8RegisterInfo::SparcV8RegisterInfo()
- : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
- SparcV8::ADJCALLSTACKUP) {}
+ : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
+ V8::ADJCALLSTACKUP) {}
int SparcV8RegisterInfo::storeRegToStackSlot(
MachineBasicBlock &MBB,
@@ -80,6 +80,9 @@ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
const TargetRegisterClass*
SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
switch (Ty->getPrimitiveID()) {
+ case Type::FloatTyID:
+ case Type::DoubleTyID:
+ assert(0 && "Floating point registers not supported yet!");
case Type::LongTyID:
case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
default: assert(0 && "Invalid type to getClass!");
@@ -90,10 +93,7 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
case Type::UShortTyID:
case Type::IntTyID:
case Type::UIntTyID:
- case Type::PointerTyID: return &GPRCInstance;
-
- case Type::FloatTyID:
- case Type::DoubleTyID: return &FPRCInstance;
+ case Type::PointerTyID: return &IntRegsInstance;
}
}
diff --git a/lib/Target/Sparc/SparcV8Instrs.td b/lib/Target/Sparc/SparcV8Instrs.td
index ac4e8be..37b4d74 100644
--- a/lib/Target/Sparc/SparcV8Instrs.td
+++ b/lib/Target/Sparc/SparcV8Instrs.td
@@ -35,6 +35,17 @@ include "SparcV8Instrs_F3.td"
// Instructions
//===----------------------------------------------------------------------===//
+// Pseudo instructions.
+def PHI : InstV8 {
+ let Name = "PHI";
+}
+def ADJCALLSTACKDOWN : InstV8 {
+ let Name = "ADJCALLSTACKDOWN";
+}
+def ADJCALLSTACKUP : InstV8 {
+ let Name = "ADJCALLSTACKUP";
+}
+
// Section B.20: SAVE and RESTORE - p117
def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
diff --git a/lib/Target/Sparc/SparcV8Instrs_F2.td b/lib/Target/Sparc/SparcV8Instrs_F2.td
index 69b0a4e..7b550bd 100644
--- a/lib/Target/Sparc/SparcV8Instrs_F2.td
+++ b/lib/Target/Sparc/SparcV8Instrs_F2.td
@@ -31,7 +31,7 @@ class F2_1<bits<3> op2Val, string name> : F2 {
let Inst{29-25} = rd;
}
-class F2_2<bits<4> cond, bits<3> op2Val, string name> : F2 {
+class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
bits<4> cond;
bit annul = 0; // currently unused
diff --git a/lib/Target/Sparc/SparcV8Instrs_F3.td b/lib/Target/Sparc/SparcV8Instrs_F3.td
index a19cd34..f1bf6a0 100644
--- a/lib/Target/Sparc/SparcV8Instrs_F3.td
+++ b/lib/Target/Sparc/SparcV8Instrs_F3.td
@@ -47,6 +47,7 @@ class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
let Inst{12-0} = simm13;
}
+/*
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name>
: F3_rs1rs2 {
bits<5> rs2;
@@ -58,4 +59,4 @@ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name>
let Inst{13-5} = opfVal;
let Inst{4-0} = rs2;
}
-
+*/ \ No newline at end of file
diff --git a/lib/Target/SparcV8/SparcV8Instrs.td b/lib/Target/SparcV8/SparcV8Instrs.td
index ac4e8be..37b4d74 100644
--- a/lib/Target/SparcV8/SparcV8Instrs.td
+++ b/lib/Target/SparcV8/SparcV8Instrs.td
@@ -35,6 +35,17 @@ include "SparcV8Instrs_F3.td"
// Instructions
//===----------------------------------------------------------------------===//
+// Pseudo instructions.
+def PHI : InstV8 {
+ let Name = "PHI";
+}
+def ADJCALLSTACKDOWN : InstV8 {
+ let Name = "ADJCALLSTACKDOWN";
+}
+def ADJCALLSTACKUP : InstV8 {
+ let Name = "ADJCALLSTACKUP";
+}
+
// Section B.20: SAVE and RESTORE - p117
def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
diff --git a/lib/Target/SparcV8/SparcV8Instrs_F2.td b/lib/Target/SparcV8/SparcV8Instrs_F2.td
index 69b0a4e..7b550bd 100644
--- a/lib/Target/SparcV8/SparcV8Instrs_F2.td
+++ b/lib/Target/SparcV8/SparcV8Instrs_F2.td
@@ -31,7 +31,7 @@ class F2_1<bits<3> op2Val, string name> : F2 {
let Inst{29-25} = rd;
}
-class F2_2<bits<4> cond, bits<3> op2Val, string name> : F2 {
+class F2_2<bits<4> condVal, bits<3> op2Val, string name> : F2 {
bits<4> cond;
bit annul = 0; // currently unused
diff --git a/lib/Target/SparcV8/SparcV8Instrs_F3.td b/lib/Target/SparcV8/SparcV8Instrs_F3.td
index a19cd34..f1bf6a0 100644
--- a/lib/Target/SparcV8/SparcV8Instrs_F3.td
+++ b/lib/Target/SparcV8/SparcV8Instrs_F3.td
@@ -47,6 +47,7 @@ class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3 {
let Inst{12-0} = simm13;
}
+/*
class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name>
: F3_rs1rs2 {
bits<5> rs2;
@@ -58,4 +59,4 @@ class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfVal, string name>
let Inst{13-5} = opfVal;
let Inst{4-0} = rs2;
}
-
+*/ \ No newline at end of file
diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index d6fd83a..7f576f9 100644
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -17,8 +17,8 @@
using namespace llvm;
SparcV8RegisterInfo::SparcV8RegisterInfo()
- : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
- SparcV8::ADJCALLSTACKUP) {}
+ : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
+ V8::ADJCALLSTACKUP) {}
int SparcV8RegisterInfo::storeRegToStackSlot(
MachineBasicBlock &MBB,
@@ -80,6 +80,9 @@ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
const TargetRegisterClass*
SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
switch (Ty->getPrimitiveID()) {
+ case Type::FloatTyID:
+ case Type::DoubleTyID:
+ assert(0 && "Floating point registers not supported yet!");
case Type::LongTyID:
case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
default: assert(0 && "Invalid type to getClass!");
@@ -90,10 +93,7 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
case Type::UShortTyID:
case Type::IntTyID:
case Type::UIntTyID:
- case Type::PointerTyID: return &GPRCInstance;
-
- case Type::FloatTyID:
- case Type::DoubleTyID: return &FPRCInstance;
+ case Type::PointerTyID: return &IntRegsInstance;
}
}
generated by cgit v1.1 at 2025-07-03 06:04:16 +0000