diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 11 | ||||
| -rw-r--r-- | test/CodeGen/X86/mul-remat.ll | 8 |
2 files changed, 14 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 3e1f942..5444016 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -169,35 +169,31 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); } - // Scalar integer multiply, multiply-high, divide, and remainder are + // Scalar integer multiply-high, divide, and remainder are // lowered to use operations that produce two results, to match the // available instructions. This exposes the two-result form to trivial // CSE, which is able to combine x/y and x%y into a single instruction, // for example. The single-result multiply instructions are introduced // in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part // is not needed. - setOperationAction(ISD::MUL , MVT::i8 , Expand); setOperationAction(ISD::MULHS , MVT::i8 , Expand); setOperationAction(ISD::MULHU , MVT::i8 , Expand); setOperationAction(ISD::SDIV , MVT::i8 , Expand); setOperationAction(ISD::UDIV , MVT::i8 , Expand); setOperationAction(ISD::SREM , MVT::i8 , Expand); setOperationAction(ISD::UREM , MVT::i8 , Expand); - setOperationAction(ISD::MUL , MVT::i16 , Expand); setOperationAction(ISD::MULHS , MVT::i16 , Expand); setOperationAction(ISD::MULHU , MVT::i16 , Expand); setOperationAction(ISD::SDIV , MVT::i16 , Expand); setOperationAction(ISD::UDIV , MVT::i16 , Expand); setOperationAction(ISD::SREM , MVT::i16 , Expand); setOperationAction(ISD::UREM , MVT::i16 , Expand); - setOperationAction(ISD::MUL , MVT::i32 , Expand); setOperationAction(ISD::MULHS , MVT::i32 , Expand); setOperationAction(ISD::MULHU , MVT::i32 , Expand); setOperationAction(ISD::SDIV , MVT::i32 , Expand); setOperationAction(ISD::UDIV , MVT::i32 , Expand); setOperationAction(ISD::SREM , MVT::i32 , Expand); setOperationAction(ISD::UREM , MVT::i32 , Expand); - setOperationAction(ISD::MUL , MVT::i64 , Expand); setOperationAction(ISD::MULHS , MVT::i64 , Expand); setOperationAction(ISD::MULHU , MVT::i64 , Expand); setOperationAction(ISD::SDIV , MVT::i64 , Expand); @@ -205,6 +201,11 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::SREM , MVT::i64 , Expand); setOperationAction(ISD::UREM , MVT::i64 , Expand); + // 8, 16, and 32-bit plain multiply are legal. And 64-bit multiply + // is also legal on x86-64. + if (!Subtarget->is64Bit()) + setOperationAction(ISD::MUL , MVT::i64 , Expand); + setOperationAction(ISD::BR_JT , MVT::Other, Expand); setOperationAction(ISD::BRCOND , MVT::Other, Custom); setOperationAction(ISD::BR_CC , MVT::Other, Expand); diff --git a/test/CodeGen/X86/mul-remat.ll b/test/CodeGen/X86/mul-remat.ll new file mode 100644 index 0000000..ffc8cc0 --- /dev/null +++ b/test/CodeGen/X86/mul-remat.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep mov | count 1 +; PR1874 + +define i32 @test(i32 %a, i32 %b) { +entry: + %tmp3 = mul i32 %b, %a + ret i32 %tmp3 +} |