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-rw-r--r--include/llvm/CodeGen/LinkAllCodegenComponents.h10
-rw-r--r--include/llvm/CodeGen/ScheduleDAG.h5
-rw-r--r--include/llvm/CodeGen/SchedulerRegistry.h1
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp3
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp3
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp12
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp8
7 files changed, 27 insertions, 15 deletions
diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h
index 22e2aae..2853500 100644
--- a/include/llvm/CodeGen/LinkAllCodegenComponents.h
+++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h
@@ -42,11 +42,11 @@ namespace {
llvm::linkOcamlGC();
llvm::linkShadowStackGC();
- (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createFastDAGScheduler(NULL, NULL, NULL, false);
- (void) llvm::createDefaultScheduler(NULL, NULL, NULL, false);
+ (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createFastDAGScheduler(NULL, NULL, NULL, NULL, false);
+ (void) llvm::createDefaultScheduler(NULL, NULL, NULL, NULL, false);
}
} ForceCodegenLinking; // Force link by creating a global definition.
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 06bb036..9e21b30 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -395,6 +395,7 @@ namespace llvm {
/// reduction list scheduler.
ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@@ -402,6 +403,7 @@ namespace llvm {
/// reduction list scheduler.
ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@@ -409,6 +411,7 @@ namespace llvm {
/// a hazard recognizer.
ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@@ -416,6 +419,7 @@ namespace llvm {
///
ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@@ -423,6 +427,7 @@ namespace llvm {
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h
index db70dee..84a0fec 100644
--- a/include/llvm/CodeGen/SchedulerRegistry.h
+++ b/include/llvm/CodeGen/SchedulerRegistry.h
@@ -35,6 +35,7 @@ class RegisterScheduler : public MachinePassRegistryNode {
public:
typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
+ const TargetMachine *,
MachineBasicBlock*, bool);
static MachinePassRegistry Registry;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 83f7b73..d205f3d 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -652,6 +652,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB, bool) {
- return new ScheduleDAGFast(*DAG, BB, DAG->getTarget());
+ return new ScheduleDAGFast(*DAG, BB, *TM);
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
index 067407b..178c3f6 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
@@ -541,8 +541,9 @@ void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) {
/// recognizer and deletes it when done.
ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB, bool Fast) {
- return new ScheduleDAGList(*DAG, BB, DAG->getTarget(),
+ return new ScheduleDAGList(*DAG, BB, *TM,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index d1617bd..5ae3158 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1881,27 +1881,29 @@ void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
if (Fast)
- return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true,
+ return new ScheduleDAGRRList(*DAG, BB, *TM, true, true,
new BURegReductionFastPriorityQueue());
- const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
- const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
+ const TargetInstrInfo *TII = TM->getInstrInfo();
+ const TargetRegisterInfo *TRI = TM->getRegisterInfo();
BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
ScheduleDAGRRList *SD =
- new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ);
+ new ScheduleDAGRRList(*DAG, BB, *TM, true, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
}
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
- return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast,
+ return new ScheduleDAGRRList(*DAG, BB, *TM, false, Fast,
new TDRegReductionPriorityQueue());
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7702b3d..3114d1b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -133,16 +133,17 @@ namespace llvm {
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
TargetLowering &TLI = IS->getTargetLowering();
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
- return createTDListDAGScheduler(IS, DAG, BB, Fast);
+ return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
} else {
assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
- return createBURRListDAGScheduler(IS, DAG, BB, Fast);
+ return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
}
}
}
@@ -1053,7 +1054,8 @@ ScheduleDAG *SelectionDAGISel::Schedule() {
RegisterScheduler::setDefault(Ctor);
}
- ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
+ TargetMachine &TM = getTargetLowering().getTargetMachine();
+ ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
Scheduler->Run();
return Scheduler;
generated by cgit v1.1 at 2025-06-06 22:12:52 +0000