diff options
| -rw-r--r-- | include/llvm/Target/Target.td | 3 | ||||
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index cc19e0d..ee9e83f 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -221,6 +221,9 @@ class Instruction { // purposes. bit isCodeGenOnly = 0; + // Is this instruction a pseudo instruction for use by the assembler parser. + bit isAsmParserOnly = 0; + InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling. string Constraints = ""; // OperandConstraint, e.g. $src = $dst. diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 94ed15b..b7085ae 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -230,6 +230,10 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables, const CodeGenInstruction &insn, InstrUID uid) { + // Ignore "asm parser only" instructions. + if (insn.TheDef->getValueAsBit("isAsmParserOnly")) + return; + RecognizableInstr recogInstr(tables, insn, uid); recogInstr.emitInstructionSpecifier(tables); |