diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 1 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 1 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCSubtarget.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/sjlj.ll | 27 |
5 files changed, 18 insertions, 25 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 4a8f59b..c9e70c8 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -270,6 +270,7 @@ def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; +let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), "mfocrf $rT, $FXM", SprMFCR>, PPC970_DGroup_First, PPC970_Unit_CRU; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 35e9935..e19be00 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -1939,6 +1939,7 @@ def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; +let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), "mfocrf $rT, $FXM", SprMFCR>, PPC970_DGroup_First, PPC970_Unit_CRU; diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index ace37c1..fd3bc2f 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -165,14 +165,7 @@ bool PPCSubtarget::enablePostRAScheduler( CodeGenOpt::Level OptLevel, TargetSubtargetInfo::AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const { - // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here, - // but we can't because we can't reassign the cr registers. There is a - // dependence between the cr register and the RLWINM instruction used - // to extract its value which the anti-dependency breaker can't currently - // see. Maybe we should make a late-expanded pseudo to encode this dependency. - // (the relevant code is in PPCDAGToDAGISel::SelectSETCC) - - Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; + Mode = TargetSubtargetInfo::ANTIDEP_ALL; CriticalPathRCs.clear(); @@ -181,9 +174,6 @@ bool PPCSubtarget::enablePostRAScheduler( else CriticalPathRCs.push_back(&PPC::GPRCRegClass); - CriticalPathRCs.push_back(&PPC::F8RCRegClass); - CriticalPathRCs.push_back(&PPC::VRRCRegClass); - return OptLevel >= CodeGenOpt::Default; } diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 097611a..b0c37b8 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 -break-anti-dependencies=none | FileCheck %s ; ModuleID = 'hh.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" target triple = "powerpc-apple-darwin9.6" diff --git a/test/CodeGen/PowerPC/sjlj.ll b/test/CodeGen/PowerPC/sjlj.ll index 410109d..414640b 100644 --- a/test/CodeGen/PowerPC/sjlj.ll +++ b/test/CodeGen/PowerPC/sjlj.ll @@ -64,15 +64,16 @@ return: ; preds = %if.end, %if.then ; CHECK: std ; Make sure that we're not saving VRSAVE on non-Darwin: ; CHECK-NOT: mfspr -; CHECK: stfd -; CHECK: stvx -; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha -; CHECK: std 31, env_sigill@toc@l([[REG]]) -; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l -; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill -; CHECK: std 1, 16([[REG]]) -; CHECK: std 2, 24([[REG]]) +; CHECK-DAG: stfd +; CHECK-DAG: stvx + +; CHECK-DAG: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha +; CHECK-DAG: std 31, env_sigill@toc@l([[REG]]) +; CHECK-DAG: addi [[REGA:[0-9]+]], [[REG]], env_sigill@toc@l +; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK-DAG: std 1, 16([[REGA]]) +; CHECK-DAG: std 2, 24([[REGA]]) ; CHECK: bcl 20, 31, .LBB1_1 ; CHECK: li 3, 1 ; CHECK: #EH_SjLj_Setup .LBB1_1 @@ -134,11 +135,11 @@ return: ; preds = %if.end, %if.then ; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha ; CHECK: std 31, env_sigill@toc@l([[REG]]) -; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l -; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill -; CHECK: std 1, 16([[REG]]) -; CHECK: std 2, 24([[REG]]) -; CHECK: std 30, 32([[REG]]) +; CHECK: addi [[REGB:[0-9]+]], [[REG]], env_sigill@toc@l +; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill +; CHECK-DAG: std 1, 16([[REGB]]) +; CHECK-DAG: std 2, 24([[REGB]]) +; CHECK-DAG: std 30, 32([[REGB]]) ; CHECK: bcl 20, 31, ; CHECK: blr |