diff options
| -rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/Disassembler/MipsDisassembler.cpp | 16 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32.txt | 6 | ||||
| -rw-r--r-- | test/MC/Disassembler/Mips/mips32_le.txt | 6 | ||||
| -rw-r--r-- | test/MC/Mips/mips-alu-instructions.s | 5 | ||||
| -rw-r--r-- | test/MC/Mips/mips64-alu-instructions.s | 6 |
7 files changed, 2 insertions, 44 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 4822106..57338df 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1071,9 +1071,6 @@ MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { - - if (!isMips64()) - return MatchOperand_NoMatch; //if the first token is not '$' we have error if (Parser.getTok().isNot(AsmToken::Dollar)) return MatchOperand_NoMatch; @@ -1091,7 +1088,7 @@ MipsAsmParser::parseHW64Regs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { MipsOperand *op = MipsOperand::CreateReg(Mips::HWR29_64, S, Parser.getTok().getLoc()); - op->setRegKind(MipsOperand::Kind_HW64Regs); + op->setRegKind(MipsOperand::Kind_HWRegs); Operands.push_back(op); Parser.Lex(); // Eat reg number diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 9560f3f..1efeffd 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -128,11 +128,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, - unsigned Insn, - uint64_t Address, - const void *Decoder); - static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -459,17 +454,6 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } -static DecodeStatus DecodeHWRegs64RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { - //Currently only hardware register 29 is supported - if (RegNo != 29) - return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64)); - return MCDisassembler::Success; -} - static DecodeStatus DecodeACRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index f93dd86..c6eb0e1 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -373,6 +373,6 @@ def HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> { let ParserMatchClass = HWRegsAsmOperand; } -def HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> { +def HW64RegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> { let ParserMatchClass = HW64RegsAsmOperand; } diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index 7022486..a193319 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -404,9 +404,3 @@ # CHECK: xori $9, $6, 17767 0x38 0xc9 0x45 0x67 - -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop -0x7c 0x05 0xe8 0x3b diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 48fa8e2..08b3672 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -404,9 +404,3 @@ # CHECK: xori $9, $6, 17767 0x67 0x45 0xc9 0x38 - -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop -0x3b 0xe8 0x05 0x7c diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index 52fd900..ee2a9a0 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -81,10 +81,6 @@ # CHECK: sub $6, $zero, $7 # encoding: [0x22,0x30,0x07,0x00] # CHECK: subu $6, $zero, $7 # encoding: [0x23,0x30,0x07,0x00] # CHECK: addu $7, $8, $zero # encoding: [0x21,0x38,0x00,0x01] -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] add $9,$6,$7 add $9,$6,17767 addu $9,$6,-15001 @@ -102,4 +98,3 @@ neg $6,$7 negu $6,$7 move $7,$8 - rdhwr $5, $29 diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index d30ddee..a77ed43 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -78,11 +78,6 @@ # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: dsubu $4, $3, $5 # encoding: [0x2f,0x20,0x65,0x00] # CHECK: daddu $7, $8, $zero # encoding: [0x2d,0x38,0x00,0x01] -# CHECK: .set push -# CHECK: .set mips32r2 -# CHECK: rdhwr $5, $29 -# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c] - dadd $9,$6,$7 dadd $9,$6,17767 daddu $9,$6,-15001 @@ -97,4 +92,3 @@ multu $3,$5 dsubu $4,$3,$5 move $7,$8 - rdhwr $5, $29 |