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-rw-r--r--include/llvm/Target/TargetLowering.h4
-rw-r--r--include/llvm/Target/TargetOptions.h6
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp4
-rw-r--r--lib/Target/X86/README.txt39
-rw-r--r--lib/Target/X86/X86.td2
-rw-r--r--lib/Target/X86/X86CallingConv.td13
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp11
-rw-r--r--lib/Target/X86/X86InstrFPStack.td2
-rw-r--r--lib/Target/X86/X86InstrInfo.td2
-rw-r--r--lib/Target/X86/X86InstrSSE.td2
-rw-r--r--lib/Target/X86/X86InstrX86-64.td2
-rw-r--r--lib/Target/X86/X86RegisterInfo.td2
12 files changed, 45 insertions, 44 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 1352eaf..e1fa226 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -861,8 +861,8 @@ public:
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
/// IsEligibleForTailCallOptimization - Check whether the call is eligible for
- /// tail call optimization. Target which want to do tail call optimization
- /// should implement this function.
+ /// tail call optimization. Targets which want to do tail call optimization
+ /// should override this function.
virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
SDOperand Ret,
SelectionDAG &DAG) const {
diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h
index dd54432..1b90d46 100644
--- a/include/llvm/Target/TargetOptions.h
+++ b/include/llvm/Target/TargetOptions.h
@@ -74,9 +74,9 @@ namespace llvm {
/// be emitted.
extern bool ExceptionHandling;
- /// PerformTailCallOpt - This flag is enabled when the -tailcallopt is
- /// specified on the commandline. When the flag is on, the target will perform
- /// tail call optimization (pop the caller's stack) providing it supports it.
+ /// PerformTailCallOpt - This flag is enabled when -tailcallopt is specified
+ /// on the commandline. When the flag is on, the target will perform tail call
+ /// optimization (pop the caller's stack) providing it supports it.
extern bool PerformTailCallOpt;
} // End llvm namespace
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index c63386c..55251c2 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -4476,7 +4476,7 @@ static void copyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
}
/// CheckDAGForTailCallsAndFixThem - This Function looks for CALL nodes in the
-/// DAG and fixes their tailcall attribute operand
+/// DAG and fixes their tailcall attribute operand.
static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
TargetLowering& TLI) {
SDNode * Ret = NULL;
@@ -4497,7 +4497,7 @@ static void CheckDAGForTailCallsAndFixThem(SelectionDAG &DAG,
cast<ConstantSDNode>(OpCall.getOperand(3))->getValue() != 0;
// If CALL node has tail call attribute set to true and the call is not
// eligible (no RET or the target rejects) the attribute is fixed to
- // false. The TargetLowering::IsEligibleForTailCallOptimization function
+ // false. The TargetLowering::IsEligibleForTailCallOptimization function
// must correctly identify tail call optimizable calls.
if (isMarkedTailCall &&
(Ret==NULL ||
diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt
index 9cb01a7..ccd15be 100644
--- a/lib/Target/X86/README.txt
+++ b/lib/Target/X86/README.txt
@@ -1352,14 +1352,15 @@ L7:
L5:
//===---------------------------------------------------------------------===//
+
Tail call optimization improvements: Tail call optimization currently
-pushes all arguments on the top of the stack (their normal place if
-that was a not tail call optimized functiong call ) before moving them
-to actual stack slot. this is done to prevent overwriting of paramters
-(see example below) that might be used, since the arguments of the
-callee overwrites callers arguments.
+pushes all arguments on the top of the stack (their normal place for
+non-tail call optimized calls) before moving them to actual stack
+slot. This is done to prevent overwriting of parameters (see example
+below) that might be used, since the arguments of the callee
+overwrites caller's arguments.
- example:
+example:
int callee(int32, int64);
int caller(int32 arg1, int32 arg2) {
@@ -1371,39 +1372,41 @@ int caller(int32 arg1, int32 arg2) {
[arg2] -> [(int64)
[RETADDR] local ]
-moving arg1 onto the stack slot of callee function would overwrite
+Moving arg1 onto the stack slot of callee function would overwrite
arg2 of the caller.
Possible optimizations:
- - only push those arguments to the top of the stack that are actual
+ - Only push those arguments to the top of the stack that are actual
parameters of the caller function and have no local value in the
- caller
+ caller.
- in above example local does not need to be pushed onto the top of
- the stack as it is definitetly not a caller's function parameter
+ In the above example local does not need to be pushed onto the top
+ of the stack as it is definitely not a caller's function
+ parameter.
- - analyse the actual parameters of the callee to see which would
- overwrite a caller paramter which is used by the callee and only
- push them onto the top of the stack
+ - Analyse the actual parameters of the callee to see which would
+ overwrite a caller parameter which is used by the callee and only
+ push them onto the top of the stack.
int callee (int32 arg1, int32 arg2);
int caller (int32 arg1, int32 arg2) {
return callee(arg1,arg2);
}
- here we don't need to write any variables to the top of the stack
- since they don't overwrite each other
+ Here we don't need to write any variables to the top of the stack
+ since they don't overwrite each other.
int callee (int32 arg1, int32 arg2);
int caller (int32 arg1, int32 arg2) {
return callee(arg2,arg1);
}
- here we need to push the arguments because they overwrite each other
+ Here we need to push the arguments because they overwrite each
+ other.
- code for lowering directly onto callers arguments:
+ Code for lowering directly onto callers arguments:
+ SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
+ SmallVector<SDOperand, 8> MemOpChains;
+
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 98362c8..423c77e 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -1,4 +1,4 @@
-//===- X86.td - Target definition file for the Intel X86 arch ---*- C++ -*-===//
+//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
diff --git a/lib/Target/X86/X86CallingConv.td b/lib/Target/X86/X86CallingConv.td
index f23e580..525967a 100644
--- a/lib/Target/X86/X86CallingConv.td
+++ b/lib/Target/X86/X86CallingConv.td
@@ -1,4 +1,4 @@
-//===- X86CallingConv.td - Calling Conventions for X86 32/64 ----*- C++ -*-===//
+//===- X86CallingConv.td - Calling Conventions X86 32/64 ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -127,7 +127,7 @@ def CC_X86_64_C : CallingConv<[
CCIfType<[v8i8, v4i16, v2i32, v1i64], CCAssignToStack<8, 8>>
]>;
-// tail call convetion (fast) one register is reserved for target address
+// Tail call convention (fast): One register is reserved for target address,
// namely R9
def CC_X86_64_TailCall : CallingConv<[
// Promote i8/i16 arguments to i32.
@@ -207,15 +207,14 @@ def CC_X86_32_C : CallingConv<[
CCDelegateTo<CC_X86_32_Common>
]>;
-/// Same as C calling convention up to nonfree ECX which is used for storing
-/// potential pointer to tail called function
+/// Same as C calling convention except for non-free ECX which is used for storing
+/// a potential pointer to the tail called function.
def CC_X86_32_TailCall : CallingConv<[
// Promote i8/i16 arguments to i32.
CCIfType<[i8, i16], CCPromoteToType<i32>>,
- // The 'nest' parameter, if any, is passed in ECX.
- CCIfNest<CCAssignToReg<[ECX]>>,
-
+ // Nested functions are currently not supported by fastcc.
+
// The first 3 integer arguments, if marked 'inreg' and if the call is not
// a vararg call, are passed in integer registers.
CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX]>>>>,
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 894faa3..b35e1e6 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1,4 +1,4 @@
-//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
+//===-- X86isellowering.cpp - X86 DAG Lowering Implementation -------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -1402,13 +1402,12 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
// * elf/pic is disabled OR
// * elf/pic enabled + callee is in module + callee has
// visibility protected or hidden
-// To ensure the stack is aligned according to platform abi pass
-// tail-call-align-stack. This makes sure that argument delta is always
-// multiples of stack alignment. (Dynamic linkers need this - darwin's dyld for
-// example)
+// To keep the stack aligned according to platform abi the function
+// GetAlignedArgumentStackSize ensures that argument delta is always multiples
+// of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
// If a tail called function callee has more arguments than the caller the
// caller needs to make sure that there is room to move the RETADDR to. This is
-// achived by reserving an area the size of the argument delta right after the
+// achieved by reserving an area the size of the argument delta right after the
// original REtADDR, but before the saved framepointer or the spilled registers
// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
// stack layout:
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index a26a4ff..8ce8cdf 100644
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -1,4 +1,4 @@
-//==- X86InstrFPStack.td - Describe the X86 Instruction Set -------*- C++ -*-=//
+//==- X86InstrFPStack.td - Describe the X86 Instruction Set --*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index a6bd3fb..6302024 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1,4 +1,4 @@
-//===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
+//===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index bbcc753..7c19473 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1,4 +1,4 @@
-//====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
+//====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td
index f501b5e..077e9dc 100644
--- a/lib/Target/X86/X86InstrX86-64.td
+++ b/lib/Target/X86/X86InstrX86-64.td
@@ -1,4 +1,4 @@
-//====- X86InstrX86-64.td - Describe the X86 Instruction Set ----*- C++ -*-===//
+//====- X86InstrX86-64.td - Describe the X86 Instr. Set ----*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index d8bbbd5..2ebc8ab 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -1,4 +1,4 @@
-//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
+//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
//
// The LLVM Compiler Infrastructure
//
generated by cgit v1.1 at 2025-02-07 03:32:22 +0000