diff options
| -rw-r--r-- | lib/Target/ARM/ARMSchedule.td | 20 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV6.td | 20 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV7.td | 41 |
3 files changed, 53 insertions, 28 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td index 6e3b00e..a5ca773 100644 --- a/lib/Target/ARM/ARMSchedule.td +++ b/lib/Target/ARM/ARMSchedule.td @@ -10,11 +10,10 @@ //===----------------------------------------------------------------------===// // Functional units across ARM processors // -def FU_iALU : FuncUnit; // Integer alu unit -def FU_iLdSt : FuncUnit; // Integer load / store unit -def FU_FpALU : FuncUnit; // FP alu unit -def FU_FpLdSt : FuncUnit; // FP load / store unit -def FU_Br : FuncUnit; // Branch unit +def FU_Pipe0 : FuncUnit; // pipeline 0 issue +def FU_Pipe1 : FuncUnit; // pipeline 1 issue +def FU_LdSt0 : FuncUnit; // pipeline 0 load/store +def FU_LdSt1 : FuncUnit; // pipeline 1 load/store //===----------------------------------------------------------------------===// // Instruction Itinerary classes used for ARM @@ -30,7 +29,16 @@ def IIC_Br : InstrItinClass; //===----------------------------------------------------------------------===// // Processor instruction itineraries. -def GenericItineraries : ProcessorItineraries<[]>; +def GenericItineraries : ProcessorItineraries<[ + InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]> +]>; + include "ARMScheduleV6.td" include "ARMScheduleV7.td" diff --git a/lib/Target/ARM/ARMScheduleV6.td b/lib/Target/ARM/ARMScheduleV6.td index 0cc5c36..f0b8116 100644 --- a/lib/Target/ARM/ARMScheduleV6.td +++ b/lib/Target/ARM/ARMScheduleV6.td @@ -11,12 +11,18 @@ // //===----------------------------------------------------------------------===// +// Single issue pipeline so every itinerary starts with FU_pipe0 def V6Itineraries : ProcessorItineraries<[ - InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>, - InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>, - InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>, - InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>, - InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>, - InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>, - InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]> + // single-cycle integer ALU + InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, + // loads have an extra cycle of latency, but are fully pipelined + InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, + // fully-pipelined stores + InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>, + // fp ALU is not pipelined + InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0]>]>, + // no delay slots, so the latency of a branch is unimportant + InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]> ]>; diff --git a/lib/Target/ARM/ARMScheduleV7.td b/lib/Target/ARM/ARMScheduleV7.td index 328bb98..30360bc 100644 --- a/lib/Target/ARM/ARMScheduleV7.td +++ b/lib/Target/ARM/ARMScheduleV7.td @@ -11,23 +11,34 @@ // //===----------------------------------------------------------------------===// +// Single issue pipeline so every itinerary starts with FU_Pipe0 def V7Itineraries : ProcessorItineraries<[ - InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>, - InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>, - InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>, - InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>, - InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>, - InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>, - InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]> + // single-cycle integer ALU + InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0]>]>, + // loads have an extra cycle of latency, but are fully pipelined + InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>, InstrStage<1, [FU_LdSt0]>]>, + // fully-pipelined stores + InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0]>]>, + InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>, + // fp ALU is not pipelined + InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0]>]>, + // no delay slots, so the latency of a branch is unimportant + InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]> ]>; - +// Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1 def CortexA8Itineraries : ProcessorItineraries<[ - InstrItinData<IIC_iALU , [InstrStage<1, [FU_iALU]>]>, - InstrItinData<IIC_iLoad , [InstrStage<2, [FU_iLdSt]>]>, - InstrItinData<IIC_iStore , [InstrStage<1, [FU_iLdSt]>]>, - InstrItinData<IIC_fpALU , [InstrStage<6, [FU_FpALU]>]>, - InstrItinData<IIC_fpLoad , [InstrStage<2, [FU_FpLdSt]>]>, - InstrItinData<IIC_fpStore , [InstrStage<1, [FU_FpLdSt]>]>, - InstrItinData<IIC_Br , [InstrStage<3, [FU_Br]>]> + // single-cycle integer ALU + InstrItinData<IIC_iALU , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>, + // loads have an extra cycle of latency, but are fully pipelined + InstrItinData<IIC_iLoad , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0]>]>, + InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_LdSt0]>]>, + // fully-pipelined stores + InstrItinData<IIC_iStore , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>, + InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>, + // fp ALU is not pipelined + InstrItinData<IIC_fpALU , [InstrStage<6, [FU_Pipe0, FU_Pipe1]>]>, + // no delay slots, so the latency of a branch is unimportant + InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]> ]>; 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