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-rw-r--r--lib/Target/CellSPU/SPUISelDAGToDAG.cpp34
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp17
-rw-r--r--test/CodeGen/CellSPU/call_indirect.ll11
-rw-r--r--test/CodeGen/CellSPU/struct_1.ll33
-rw-r--r--test/CodeGen/CellSPU/struct_2.ll122
5 files changed, 199 insertions, 18 deletions
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index bb3b100..167d3c3 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -456,8 +456,9 @@ SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
const SDOperand Op0 = N.getOperand(0); // Frame index/base
const SDOperand Op1 = N.getOperand(1); // Offset within base
- if (Op1.getOpcode() == ISD::Constant
- || Op1.getOpcode() == ISD::TargetConstant) {
+ if ((Op1.getOpcode() == ISD::Constant
+ || Op1.getOpcode() == ISD::TargetConstant)
+ && Op0.getOpcode() != SPUISD::XFormAddr) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
assert(CN != 0 && "SelectDFormAddr: Expected a constant");
@@ -499,12 +500,19 @@ SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
} else
return false;
} else if (Opc == SPUISD::DFormAddr) {
- // D-Form address: This is pretty straightforward, naturally...
- ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
- assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
- Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
- Index = N.getOperand(0);
- return true;
+ // D-Form address: This is pretty straightforward,
+ // naturally... but make sure that this isn't a D-form address
+ // with a X-form address embedded within:
+ const SDOperand Op0 = N.getOperand(0); // Frame index/base
+ const SDOperand Op1 = N.getOperand(1); // Offset within base
+
+ if (Op0.getOpcode() != SPUISD::XFormAddr) {
+ ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
+ assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
+ Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
+ Index = Op0;
+ return true;
+ }
} else if (Opc == ISD::FrameIndex) {
// Stack frame index must be less than 512 (divided by 16):
FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
@@ -564,6 +572,12 @@ SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
Base = N;
Index = N.getOperand(1);
return true;
+ } else if (Opc == SPUISD::DFormAddr) {
+ // Must be a D-form address with an X-form address embedded
+ // within:
+ Base = N.getOperand(0);
+ Index = N.getOperand(1);
+ return true;
} else if (N.getNumOperands() == 2) {
SDOperand N1 = N.getOperand(0);
SDOperand N2 = N.getOperand(1);
@@ -578,14 +592,14 @@ SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
/*UNREACHED*/
} else {
cerr << "SelectXFormAddr: 2-operand unhandled operand:\n";
- N.Val->dump();
+ N.Val->dump(CurDAG);
cerr << "\n";
abort();
/*UNREACHED*/
}
} else {
cerr << "SelectXFormAddr: Unhandled operand type:\n";
- N.Val->dump();
+ N.Val->dump(CurDAG);
cerr << "\n";
abort();
/*UNREACHED*/
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 59e2068..706eea9 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -90,13 +90,11 @@ namespace {
const unsigned Opc = Op.getOpcode();
return (Opc == ISD::GlobalAddress
|| Opc == ISD::GlobalTLSAddress
- /* || Opc == ISD::FrameIndex */
|| Opc == ISD::JumpTable
|| Opc == ISD::ConstantPool
|| Opc == ISD::ExternalSymbol
|| Opc == ISD::TargetGlobalAddress
|| Opc == ISD::TargetGlobalTLSAddress
- /* || Opc == ISD::TargetFrameIndex */
|| Opc == ISD::TargetJumpTable
|| Opc == ISD::TargetConstantPool
|| Opc == ISD::TargetExternalSymbol
@@ -566,7 +564,7 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// Rotate the chunk if necessary
if (rotamt < 0)
rotamt += 16;
- if (rotamt != 0) {
+ if (rotamt != 0 || !was16aligned) {
SDVTList vecvts = DAG.getVTList(MVT::v16i8, MVT::Other);
if (was16aligned) {
@@ -574,10 +572,12 @@ LowerLOAD(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
Ops[1] = result;
Ops[2] = DAG.getConstant(rotamt, MVT::i16);
} else {
+ MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
LoadSDNode *LN1 = cast<LoadSDNode>(result);
Ops[0] = the_chain;
Ops[1] = result;
- Ops[2] = LN1->getBasePtr();
+ Ops[2] = DAG.getNode(ISD::ADD, PtrVT, LN1->getBasePtr(),
+ DAG.getConstant(rotamt, PtrVT));
}
result = DAG.getNode(SPUISD::ROTBYTES_LEFT_CHAINED, vecvts, Ops, 3);
@@ -690,7 +690,6 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
}
chunk_offset &= 0xf;
- chunk_offset /= (MVT::getSizeInBits(StVT == MVT::i1 ? (unsigned) MVT::i8 : StVT) / 8);
SDOperand insertEltOffs = DAG.getConstant(chunk_offset, PtrVT);
SDOperand insertEltPtr;
@@ -700,10 +699,18 @@ LowerSTORE(SDOperand Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// a new D-form address with a slot offset and the orignal base pointer.
// Otherwise generate a D-form address with the slot offset relative
// to the stack pointer, which is always aligned.
+ DEBUG(cerr << "CellSPU LowerSTORE: basePtr = ");
+ DEBUG(basePtr.Val->dump(&DAG));
+ DEBUG(cerr << "\n");
+
if (basePtr.getOpcode() == SPUISD::DFormAddr) {
insertEltPtr = DAG.getNode(SPUISD::DFormAddr, PtrVT,
basePtr.getOperand(0),
insertEltOffs);
+ } else if (basePtr.getOpcode() == SPUISD::XFormAddr ||
+ (basePtr.getOpcode() == ISD::ADD
+ && basePtr.getOperand(0).getOpcode() == SPUISD::XFormAddr)) {
+ insertEltPtr = basePtr;
} else {
insertEltPtr = DAG.getNode(SPUISD::DFormAddr, PtrVT,
DAG.getRegister(SPU::R1, PtrVT),
diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll
index 7aa8abc..27157ca 100644
--- a/test/CodeGen/CellSPU/call_indirect.ll
+++ b/test/CodeGen/CellSPU/call_indirect.ll
@@ -1,10 +1,21 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep bisl %t1.s | count 6 &&
; RUN: grep ila %t1.s | count 1 &&
; RUN: grep rotqbyi %t1.s | count 4 &&
; RUN: grep lqa %t1.s | count 4 &&
; RUN: grep lqd %t1.s | count 6 &&
; RUN: grep dispatch_tab %t1.s | count 10
+; RUN: grep bisl %t2.s | count 6 &&
+; RUN: grep ilhu %t2.s | count 1 &&
+; RUN: grep iohl %t2.s | count 1 &&
+; RUN: grep rotqby %t2.s | count 5 &&
+; RUN: grep lqd %t2.s | count 12 &&
+; RUN: grep lqx %t2.s | count 6 &&
+; RUN: grep il %t2.s | count 7 &&
+; RUN: grep ai %t2.s | count 5 &&
+; RUN: grep dispatch_tab %t2.s | count 7
+
; ModuleID = 'call_indirect.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
target triple = "spu-unknown-elf"
diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll
index 1159b55..a28520c 100644
--- a/test/CodeGen/CellSPU/struct_1.ll
+++ b/test/CodeGen/CellSPU/struct_1.ll
@@ -1,14 +1,27 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep lqa %t1.s | count 10 &&
-; RUN: grep lqd %t1.s | count 2 &&
+; RUN: grep lqd %t1.s | count 4 &&
; RUN: grep rotqbyi %t1.s | count 5 &&
; RUN: grep xshw %t1.s | count 1 &&
; RUN: grep andi %t1.s | count 4 &&
; RUN: grep cbd %t1.s | count 3 &&
; RUN: grep chd %t1.s | count 1 &&
-; RUN: grep cwd %t1.s | count 1 &&
-; RUN: grep shufb %t1.s | count 5 &&
+; RUN: grep cwd %t1.s | count 3 &&
+; RUN: grep shufb %t1.s | count 7 &&
; RUN: grep stqa %t1.s | count 5
+; RUN: grep iohl %t2.s | count 14 &&
+; RUN: grep ilhu %t2.s | count 14 &&
+; RUN: grep lqx %t2.s | count 14 &&
+; RUN: grep rotqbyi %t2.s | count 5 &&
+; RUN: grep xshw %t2.s | count 1 &&
+; RUN: grep andi %t2.s | count 4 &&
+; RUN: grep cbd %t2.s | count 3 &&
+; RUN: grep chd %t2.s | count 1 &&
+; RUN: grep cwd %t2.s | count 3 &&
+; RUN: grep shufb %t2.s | count 7 &&
+; RUN: grep stqx %t2.s | count 7
+
; ModuleID = 'struct_1.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
@@ -105,3 +118,17 @@ entry:
store i16 %s, i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16
ret void
}
+
+define void @set_hackstate_i3(i32 %i) {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 11), align 16
+ ret void
+}
+
+
+define void @set_hackstate_i6(i32 %i) {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 16
+ ret void
+}
+
diff --git a/test/CodeGen/CellSPU/struct_2.ll b/test/CodeGen/CellSPU/struct_2.ll
new file mode 100644
index 0000000..3c2484c
--- /dev/null
+++ b/test/CodeGen/CellSPU/struct_2.ll
@@ -0,0 +1,122 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep lqx %t1.s | count 14 &&
+; RUN: grep rotqby %t1.s | count 7 &&
+; RUN: grep xshw %t1.s | count 1 &&
+; RUN: grep andi %t1.s | count 4 &&
+; RUN: grep cbx %t1.s | count 1 &&
+; RUN: grep cbd %t1.s | count 2 &&
+; RUN: grep chd %t1.s | count 1 &&
+; RUN: grep cwd %t1.s | count 3 &&
+; RUN: grep shufb %t1.s | count 7 &&
+; RUN: grep stqx %t1.s | count 7
+
+; ModuleID = 'struct_1.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+; struct hackstate {
+; unsigned char c1; // offset 0 (rotate left by 13 bytes to byte 3)
+; unsigned char c2; // offset 1 (rotate left by 14 bytes to byte 3)
+; unsigned char c3; // offset 2 (rotate left by 15 bytes to byte 3)
+; int i1; // offset 4 (rotate left by 4 bytes to byte 0)
+; short s1; // offset 8 (rotate left by 6 bytes to byte 2)
+; int i2; // offset 12 [ignored]
+; unsigned char c4; // offset 16 [ignored]
+; unsigned char c5; // offset 17 [ignored]
+; unsigned char c6; // offset 18 [ignored]
+; unsigned char c7; // offset 19 (no rotate, in preferred slot)
+; int i3; // offset 20 [ignored]
+; int i4; // offset 24 [ignored]
+; int i5; // offset 28 [ignored]
+; int i6; // offset 32 (no rotate, in preferred slot)
+; }
+%struct.hackstate = type { i8, i8, i8, i32, i16, i32, i8, i8, i8, i8, i32, i32, i32, i32 }
+
+; struct hackstate state = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+@state = global %struct.hackstate zeroinitializer, align 4
+
+define i8 @get_hackstate_c1() zeroext {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 4
+ ret i8 %tmp2
+}
+
+define i8 @get_hackstate_c2() zeroext {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 4
+ ret i8 %tmp2
+}
+
+define i8 @get_hackstate_c3() zeroext {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 4
+ ret i8 %tmp2
+}
+
+define i32 @get_hackstate_i1() {
+entry:
+ %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 4
+ ret i32 %tmp2
+}
+
+define i16 @get_hackstate_s1() signext {
+entry:
+ %tmp2 = load i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 4
+ ret i16 %tmp2
+}
+
+define i8 @get_hackstate_c7() zeroext {
+entry:
+ %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 9), align 4
+ ret i8 %tmp2
+}
+
+define i32 @get_hackstate_i6() zeroext {
+entry:
+ %tmp2 = load i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 4
+ ret i32 %tmp2
+}
+
+define void @set_hackstate_c1(i8 zeroext %c) {
+entry:
+ store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 4
+ ret void
+}
+
+define void @set_hackstate_c2(i8 zeroext %c) {
+entry:
+ store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 4
+ ret void
+}
+
+define void @set_hackstate_c3(i8 zeroext %c) {
+entry:
+ store i8 %c, i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 4
+ ret void
+}
+
+define void @set_hackstate_i1(i32 %i) {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 3), align 4
+ ret void
+}
+
+define void @set_hackstate_s1(i16 signext %s) {
+entry:
+ store i16 %s, i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 4
+ ret void
+}
+
+define void @set_hackstate_i3(i32 %i) {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 11), align 4
+ ret void
+}
+
+
+define void @set_hackstate_i6(i32 %i) {
+entry:
+ store i32 %i, i32* getelementptr (%struct.hackstate* @state, i32 0, i32 13), align 4
+ ret void
+}
+
generated by cgit v1.1 at 2025-01-19 03:57:55 +0000