diff options
-rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 7 | ||||
-rw-r--r-- | lib/CodeGen/RegAllocPBQP.cpp | 3 | ||||
-rw-r--r-- | lib/CodeGen/VirtRegMap.cpp | 58 | ||||
-rw-r--r-- | lib/CodeGen/VirtRegMap.h | 23 |
4 files changed, 63 insertions, 28 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 8c20a63..e8296a7 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -105,7 +105,7 @@ namespace { greater_ptr<LiveInterval> > IntervalHeap; IntervalHeap unhandled_; std::auto_ptr<PhysRegTracker> prt_; - std::auto_ptr<VirtRegMap> vrm_; + VirtRegMap* vrm_; std::auto_ptr<Spiller> spiller_; public: @@ -126,6 +126,8 @@ namespace { AU.addPreserved<LiveStacks>(); AU.addRequired<MachineLoopInfo>(); AU.addPreserved<MachineLoopInfo>(); + AU.addRequired<VirtRegMap>(); + AU.addPreserved<VirtRegMap>(); AU.addPreservedID(MachineDominatorsID); MachineFunctionPass::getAnalysisUsage(AU); } @@ -305,7 +307,7 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) { ComputeRelatedRegClasses(); if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_)); - vrm_.reset(new VirtRegMap(*mf_)); + vrm_ = &getAnalysis<VirtRegMap>(); if (!spiller_.get()) spiller_.reset(createSpiller()); initIntervalSets(); @@ -314,7 +316,6 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) { // Rewrite spill code and update the PhysRegsUsed set. spiller_->runOnMachineFunction(*mf_, *vrm_); - vrm_.reset(); // Free the VirtRegMap assert(unhandled_.empty() && "Unhandled live intervals remain!"); fixed_.clear(); diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index 767e985..7f699f8 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -799,8 +799,7 @@ bool PBQPRegAlloc::runOnMachineFunction(MachineFunction &MF) { lss = &getAnalysis<LiveStacks>(); loopInfo = &getAnalysis<MachineLoopInfo>(); - std::auto_ptr<VirtRegMap> vrmAutoPtr(new VirtRegMap(*mf)); - vrm = vrmAutoPtr.get(); + vrm = &getAnalysis<VirtRegMap>(); DOUT << "PBQP Register Allocating for " << mf->getFunction()->getName() << "\n"; diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 0bfbded..2c7037c 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -43,20 +43,42 @@ STATISTIC(NumSpills , "Number of register spills"); // VirtRegMap implementation //===----------------------------------------------------------------------===// -VirtRegMap::VirtRegMap(MachineFunction &mf) - : TII(*mf.getTarget().getInstrInfo()), MF(mf), - Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT), - Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), - Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1), - LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { +char VirtRegMap::ID = 0; + +static RegisterPass<VirtRegMap> +X("virtregmap", "Virtual Register Map"); + +bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) { + TII = mf.getTarget().getInstrInfo(); + MF = &mf; + + ReMatId = MAX_STACK_SLOT+1; + LowSpillSlot = HighSpillSlot = NO_STACK_SLOT; + + Virt2PhysMap.clear(); + Virt2StackSlotMap.clear(); + Virt2ReMatIdMap.clear(); + Virt2SplitMap.clear(); + Virt2SplitKillMap.clear(); + ReMatMap.clear(); + ImplicitDefed.clear(); + SpillSlotToUsesMap.clear(); + MI2VirtMap.clear(); + SpillPt2VirtMap.clear(); + RestorePt2VirtMap.clear(); + EmergencySpillMap.clear(); + EmergencySpillSlots.clear(); + SpillSlotToUsesMap.resize(8); - ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1- + ImplicitDefed.resize(MF->getRegInfo().getLastVirtReg()+1- TargetRegisterInfo::FirstVirtualRegister); grow(); + + return false; } void VirtRegMap::grow() { - unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg(); + unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg(); Virt2PhysMap.grow(LastVirtReg); Virt2StackSlotMap.grow(LastVirtReg); Virt2ReMatIdMap.grow(LastVirtReg); @@ -70,8 +92,8 @@ int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); - const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); - int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); + int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment()); if (LowSpillSlot == NO_STACK_SLOT) LowSpillSlot = SS; @@ -90,7 +112,7 @@ void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) { assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); assert((SS >= 0 || - (SS >= MF.getFrameInfo()->getObjectIndexBegin())) && + (SS >= MF->getFrameInfo()->getObjectIndexBegin())) && "illegal fixed frame index"); Virt2StackSlotMap[virtReg] = SS; } @@ -115,7 +137,7 @@ int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { EmergencySpillSlots.find(RC); if (I != EmergencySpillSlots.end()) return I->second; - int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment()); if (LowSpillSlot == NO_STACK_SLOT) LowSpillSlot = SS; @@ -126,7 +148,7 @@ int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { } void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) { - if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) { + if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) { // If FI < LowSpillSlot, this stack reference was produced by // instruction selection and is not a spill if (FI >= LowSpillSlot) { @@ -163,7 +185,7 @@ void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { if (!MO.isFI()) continue; int FI = MO.getIndex(); - if (MF.getFrameInfo()->isFixedObjectIndex(FI)) + if (MF->getFrameInfo()->isFixedObjectIndex(FI)) continue; // This stack reference was produced by instruction selection and // is not a spill @@ -179,19 +201,19 @@ void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) { EmergencySpillMap.erase(MI); } -void VirtRegMap::print(std::ostream &OS) const { - const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); +void VirtRegMap::print(std::ostream &OS, const Module* M) const { + const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo(); OS << "********** REGISTER MAP **********\n"; for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, - e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { + e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) { if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n"; } for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, - e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) + e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; OS << '\n'; diff --git a/lib/CodeGen/VirtRegMap.h b/lib/CodeGen/VirtRegMap.h index 7627d67..2e9c899 100644 --- a/lib/CodeGen/VirtRegMap.h +++ b/lib/CodeGen/VirtRegMap.h @@ -17,6 +17,7 @@ #ifndef LLVM_CODEGEN_VIRTREGMAP_H #define LLVM_CODEGEN_VIRTREGMAP_H +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/IndexedMap.h" @@ -30,7 +31,7 @@ namespace llvm { class MachineFunction; class TargetInstrInfo; - class VirtRegMap { + class VirtRegMap : public MachineFunctionPass { public: enum { NO_PHYS_REG = 0, @@ -43,9 +44,9 @@ namespace llvm { std::pair<unsigned, ModRef> > MI2VirtMapTy; private: - const TargetInstrInfo &TII; + const TargetInstrInfo *TII; - MachineFunction &MF; + MachineFunction *MF; /// Virt2PhysMap - This is a virtual to physical register /// mapping. Each virtual register is required to have an entry in /// it; even spilled virtual registers (the register mapped to a @@ -125,7 +126,19 @@ namespace llvm { void operator=(const VirtRegMap&); // DO NOT IMPLEMENT public: - explicit VirtRegMap(MachineFunction &mf); + static char ID; + VirtRegMap() : MachineFunctionPass(&ID), Virt2PhysMap(NO_PHYS_REG), + Virt2StackSlotMap(NO_STACK_SLOT), + Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0), + Virt2SplitKillMap(0), ReMatMap(NULL), + ReMatId(MAX_STACK_SLOT+1), + LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) { } + virtual bool runOnMachineFunction(MachineFunction &MF); + + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); + } void grow(); @@ -417,7 +430,7 @@ namespace llvm { /// the folded instruction map and spill point map. void RemoveMachineInstrFromMaps(MachineInstr *MI); - void print(std::ostream &OS) const; + void print(std::ostream &OS, const Module* M = 0) const; void print(std::ostream *OS) const { if (OS) print(*OS); } void dump() const; }; |