diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/PIC16/PIC16AsmPrinter.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/PIC16/PIC16ISelLowering.cpp | 14 | ||||
| -rw-r--r-- | lib/Target/PIC16/PIC16ISelLowering.h | 2 | ||||
| -rw-r--r-- | lib/Target/PIC16/PIC16InstrInfo.td | 7 |
5 files changed, 35 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 888eeda..8d1ea8d 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1314,6 +1314,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { } break; } + case TargetLowering::Custom: + Result = TLI.LowerOperation(Op, DAG); + if (Result.getNode()) + break; case TargetLowering::Legal: { LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); if (Action == Legal && Tmp1 == Node->getOperand(0)) diff --git a/lib/Target/PIC16/PIC16AsmPrinter.cpp b/lib/Target/PIC16/PIC16AsmPrinter.cpp index 6a5c2e0..b495043 100644 --- a/lib/Target/PIC16/PIC16AsmPrinter.cpp +++ b/lib/Target/PIC16/PIC16AsmPrinter.cpp @@ -21,6 +21,8 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Mangler.h" +#include "llvm/CodeGen/DwarfWriter.h" +#include "llvm/CodeGen/MachineModuleInfo.h" using namespace llvm; @@ -187,6 +189,12 @@ bool PIC16AsmPrinter::doInitialization (Module &M) { // The processor should be passed to llc as in input and the header file // should be generated accordingly. O << "\t#include P16F1937.INC\n"; + MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>(); + assert(MMI); + DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>(); + assert(DW && "Dwarf Writer is not available"); + DW->BeginModule(&M, MMI, O, this, TAI); + EmitExternsAndGlobals (M); EmitInitData (M); EmitUnInitData(M); diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index cbe3a9d..d50f57f 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -137,6 +137,8 @@ PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM) //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom); setTruncStoreAction(MVT::i16, MVT::i8, Custom); + setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Custom); + // Now deduce the information based on the above mentioned // actions computeRegisterProperties(); @@ -258,6 +260,7 @@ const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const { case PIC16ISD::SELECT_ICC: return "PIC16ISD::SELECT_ICC"; case PIC16ISD::BRCOND: return "PIC16ISD::BRCOND"; case PIC16ISD::Dummy: return "PIC16ISD::Dummy"; + case PIC16ISD::PIC16StopPoint: return "PIC16ISD::PIC16StopPoint"; } } @@ -808,10 +811,21 @@ SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { return LowerBR_CC(Op, DAG); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); + case ISD::DBG_STOPPOINT: + return LowerStopPoint(Op, DAG); } return SDValue(); } +SDValue PIC16TargetLowering::LowerStopPoint(SDValue Op, SelectionDAG &DAG) { + DbgStopPointSDNode *SP = dyn_cast<DbgStopPointSDNode>(Op); + unsigned line = SP->getLine(); + SDValue LineNode = DAG.getConstant(line, MVT::i8); + DebugLoc dl = Op.getDebugLoc(); + return DAG.getNode(PIC16ISD::PIC16StopPoint, dl, MVT::Other, + Op.getOperand(0), LineNode); +} + SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl) { diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h index b2a89db..3dae352 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.h +++ b/lib/Target/PIC16/PIC16ISelLowering.h @@ -48,6 +48,7 @@ namespace llvm { SUBCC, // Compare for equality or inequality. SELECT_ICC, // Psuedo to be caught in schedular and expanded to brcond. BRCOND, // Conditional branch. + PIC16StopPoint, Dummy }; @@ -91,6 +92,7 @@ namespace llvm { SDValue InFlag, SelectionDAG &DAG); SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); + SDValue LowerStopPoint(SDValue Op, SelectionDAG &DAG); SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC, SelectionDAG &DAG, DebugLoc dl); virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, diff --git a/lib/Target/PIC16/PIC16InstrInfo.td b/lib/Target/PIC16/PIC16InstrInfo.td index 471180f..85dc828 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.td +++ b/lib/Target/PIC16/PIC16InstrInfo.td @@ -67,6 +67,9 @@ def PIC16callseq_start : SDNode<"ISD::CALLSEQ_START", SDTI8VoidOp, def PIC16callseq_end : SDNode<"ISD::CALLSEQ_END", SDTI8VoidOp, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; +def PIC16StopPoint : SDNode<"PIC16ISD::PIC16StopPoint", SDTI8VoidOp, + [SDNPHasChain]>; + // Low 8-bits of GlobalAddress. def PIC16Lo : SDNode<"PIC16ISD::Lo", SDTI8UnaryOp>; @@ -160,6 +163,10 @@ class BinOpLW<bits<6> opcode, string OpcStr, SDNode OpNode> : // PIC16 Instructions. //===----------------------------------------------------------------------===// +def line_directive : ByteFormat<0, (outs), (ins i8imm:$src), + ".line $src", + [(PIC16StopPoint (i8 imm:$src))]>; + // Pseudo-instructions. def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i8imm:$amt), "!ADJCALLSTACKDOWN $amt", |