diff options
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 11 | ||||
| -rw-r--r-- | test/CodeGen/X86/smul-with-overflow-2.ll | 20 |
2 files changed, 31 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 9649c23..f4a57be 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -3612,6 +3612,17 @@ def : Pat<(parallel (X86smul_ovf (load addr:$src1), i32immSExt8:$src2), (implicit EFLAGS)), (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>; +// Optimize multiple with overflow by 2. +let AddedComplexity = 2 in { +def : Pat<(parallel (X86smul_ovf GR16:$src1, 2), + (implicit EFLAGS)), + (ADD16rr GR16:$src1, GR16:$src1)>; + +def : Pat<(parallel (X86smul_ovf GR32:$src1, 2), + (implicit EFLAGS)), + (ADD32rr GR32:$src1, GR32:$src1)>; +} + //===----------------------------------------------------------------------===// // Floating Point Stack Support //===----------------------------------------------------------------------===// diff --git a/test/CodeGen/X86/smul-with-overflow-2.ll b/test/CodeGen/X86/smul-with-overflow-2.ll new file mode 100644 index 0000000..c3dbfd7 --- /dev/null +++ b/test/CodeGen/X86/smul-with-overflow-2.ll @@ -0,0 +1,20 @@ +; RUN: llvm-as < %s | llc -march=x86 | grep mul | count 1 +; RUN: llvm-as < %s | llc -march=x86 | grep add | count 3 + +define i32 @t1(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +} + +define i32 @t2(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +} + +declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) nounwind |