diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index bf84993..3f7f9f7 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1183,7 +1183,10 @@ X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) { RC = X86::FR64RegisterClass; else { assert(MVT::isVector(RegVT)); - RC = X86::VR128RegisterClass; + if (MVT::getSizeInBits(RegVT) == 64) + RC = X86::VR64RegisterClass; + else + RC = X86::VR128RegisterClass; } unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC); |