diff options
| -rw-r--r-- | lib/Target/Hexagon/HexagonRegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsFrameLowering.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.cpp | 16 |
3 files changed, 13 insertions, 10 deletions
diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index f8ffdc4..2c23674 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -189,7 +189,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, (MI.getOpcode() == Hexagon::LDriw_f) || (MI.getOpcode() == Hexagon::LDrid_f)) { unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ? - *getSubRegisters(MI.getOperand(0).getReg()) : + getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) : MI.getOperand(0).getReg(); // Check if offset can fit in addi. diff --git a/lib/Target/Mips/MipsFrameLowering.cpp b/lib/Target/Mips/MipsFrameLowering.cpp index 98c91b1..27609c1 100644 --- a/lib/Target/Mips/MipsFrameLowering.cpp +++ b/lib/Target/Mips/MipsFrameLowering.cpp @@ -196,11 +196,10 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { // If Reg is a double precision register, emit two cfa_offsets, // one for each of the paired single precision registers. if (Mips::AFGR64RegClass.contains(Reg)) { - const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg); MachineLocation DstML0(MachineLocation::VirtualFP, Offset); MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); - MachineLocation SrcML0(*SubRegs); - MachineLocation SrcML1(*(SubRegs + 1)); + MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven)); + MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd)); if (!STI.isLittle()) std::swap(SrcML0, SrcML1); diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index e2e9d87..c01830d 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -240,9 +240,12 @@ void MipsInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB, unsigned N = I->getOperand(2).getImm(); const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); DebugLoc dl = I->getDebugLoc(); - const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); - BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N)); + assert(N < 2 && "Invalid immediate"); + unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven; + unsigned SubReg = TM.getRegisterInfo()->getSubReg(SrcReg, SubIdx); + + BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg); } void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB, @@ -252,13 +255,14 @@ void MipsInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB, unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); DebugLoc dl = I->getDebugLoc(); - const uint16_t* SubReg = - TM.getRegisterInfo()->getSubRegisters(DstReg); + const TargetRegisterInfo *TRI = TM.getRegisterInfo(); // mtc1 Lo, $fp // mtc1 Hi, $fp + 1 - BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg); - BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg); + BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpeven)) + .addReg(LoReg); + BuildMI(MBB, I, dl, Mtc1Tdd, TRI->getSubReg(DstReg, Mips::sub_fpodd)) + .addReg(HiReg); } bool MipsInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { |