diff options
| -rw-r--r-- | lib/CodeGen/LLVMTargetMachine.cpp | 10 | ||||
| -rw-r--r-- | lib/Transforms/Scalar/GVN.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/lsr-code-insertion.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/2006-05-11-InstrSched.ll | 2 |
4 files changed, 11 insertions, 5 deletions
diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index f29944c..7def8fa 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -38,6 +38,11 @@ static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden, static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, cl::desc("Dump garbage collector data")); +// Hidden options to help debugging +static cl::opt<bool> +EnableSinking("enable-sinking", cl::init(false), cl::Hidden, + cl::desc("Perform sinking on machine code")); + // When this works it will be on by default. static cl::opt<bool> DisablePostRAScheduler("disable-post-RA-scheduler", @@ -178,10 +183,11 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) { if (PrintMachineCode) PM.add(createMachineFunctionPrinterPass(cerr)); - if (!Fast) { + if (!Fast) PM.add(createMachineLICMPass()); + + if (EnableSinking) PM.add(createMachineSinkingPass()); - } // Run pre-ra passes. if (addPreRegAlloc(PM, Fast) && PrintMachineCode) diff --git a/lib/Transforms/Scalar/GVN.cpp b/lib/Transforms/Scalar/GVN.cpp index 9c7f904..308264a 100644 --- a/lib/Transforms/Scalar/GVN.cpp +++ b/lib/Transforms/Scalar/GVN.cpp @@ -48,7 +48,7 @@ STATISTIC(NumPRELoad, "Number of loads PRE'd"); static cl::opt<bool> EnablePRE("enable-pre", cl::init(true), cl::Hidden); -cl::opt<bool> EnableLoadPRE("enable-load-pre"/*, cl::init(true)*/); +cl::opt<bool> EnableLoadPRE("enable-load-pre", cl::init(true)); //===----------------------------------------------------------------------===// // ValueTable Class diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index 0a92279..3881e91 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | llc -stats |& grep {40.*Number of machine instrs printed} +; RUN: llvm-as < %s | llc -stats |& grep {39.*Number of machine instrs printed} ; RUN: llvm-as < %s | llc -stats |& grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize diff --git a/test/CodeGen/X86/2006-05-11-InstrSched.ll b/test/CodeGen/X86/2006-05-11-InstrSched.ll index 774e724..9d1d324 100644 --- a/test/CodeGen/X86/2006-05-11-InstrSched.ll +++ b/test/CodeGen/X86/2006-05-11-InstrSched.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -realign-stack=0 |&\ -; RUN: grep {asm-printer} | grep 31 +; RUN: grep {asm-printer} | grep 32 target datalayout = "e-p:32:32" define void @foo(i32* %mc, i32* %bp, i32* %ms, i32* %xmb, i32* %mpp, i32* %tpmm, i32* %ip, i32* %tpim, i32* %dpp, i32* %tpdm, i32* %bpi, i32 %M) nounwind { |