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-rw-r--r--include/llvm/CodeGen/SelectionDAG.h1
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp15
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp10
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp2
6 files changed, 15 insertions, 29 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index a0dff6a..c466cf9 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -379,7 +379,6 @@ public:
SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT SrcTy);
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
- SDValue getNOT(SDValue Val, MVT VT);
SDValue getNOT(DebugLoc DL, SDValue Val, MVT VT);
/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 8eae470..604432b 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2845,15 +2845,15 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
}
// fold (select C, 0, X) -> (and (not C), X)
if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
- SDValue NOTNode = DAG.getNOT(N0, VT);
+ SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
- return DAG.getNode(ISD::AND, VT, NOTNode, N2);
+ return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
}
// fold (select C, X, 1) -> (or (not C), X)
if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
- return DAG.getNode(ISD::OR, VT, NOTNode, N1);
+ return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
}
// fold (select C, X, 0) -> (and C, X)
if (VT == MVT::i1 && N2C && N2C->isNullValue())
@@ -5739,7 +5739,7 @@ SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
N0);
- SDValue NotN0 = DAG.getNOT(N0, XType);
+ SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
return DAG.getNode(ISD::SRL, XType,
DAG.getNode(ISD::AND, XType, NegN0, NotN0),
DAG.getConstant(XType.getSizeInBits()-1,
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index eba252f..5ae6364 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -6321,7 +6321,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
}
- Op = DAG.getNOT(Op, VT);
+ Op = DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT);
return DAG.getNode(ISD::CTPOP, VT, Op);
}
case ISD::CTTZ: {
@@ -6330,8 +6330,10 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
MVT VT = Op.getValueType();
- SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT),
- DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
+ SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
+ DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT),
+ DAG.getNode(ISD::SUB, VT, Op,
+ DAG.getConstant(1, VT)));
// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index d3a59b4..bb1c728 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -841,21 +841,6 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
///
-SDValue SelectionDAG::getNOT(SDValue Val, MVT VT) {
- SDValue NegOne;
- if (VT.isVector()) {
- MVT EltVT = VT.getVectorElementType();
- SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
- std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
- NegOne = getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0], NegOnes.size());
- } else
- NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
-
- return getNode(ISD::XOR, VT, Val, NegOne);
-}
-
-/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
-///
SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
SDValue NegOne;
if (VT.isVector()) {
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 1f9d9cf..ebc5067 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1841,7 +1841,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
default: assert(0 && "Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
- N0 = DAG.getNOT(Temp, MVT::i1);
+ N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
@@ -1850,28 +1850,28 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
break;
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
- Temp = DAG.getNOT(N0, MVT::i1);
+ Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1);
N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
- Temp = DAG.getNOT(N1, MVT::i1);
+ Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1);
N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
- Temp = DAG.getNOT(N0, MVT::i1);
+ Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1);
N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
- Temp = DAG.getNOT(N1, MVT::i1);
+ Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1);
N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
break;
}
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index e17ae99..2aa2e4a 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5280,7 +5280,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
// If the logical-not of the result is required, perform that now.
if (Invert)
- Result = DAG.getNOT(Result, VT);
+ Result = DAG.getNOT(Op.getDebugLoc(), Result, VT);
return Result;
}
generated by cgit v1.1 at 2024-10-28 00:31:52 +0000