diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2009-11-02-NegativeLane.ll | 14 |
2 files changed, 14 insertions, 7 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 0ea46af..d575e8a 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6413,6 +6413,13 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { break; } + // If the vector element type is not legal, the BUILD_VECTOR operands + // are promoted and implicitly truncated. Make that explicit here. + if (LHSOp.getValueType() != EltType) + LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp); + if (RHSOp.getValueType() != EltType) + RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp); + SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType, LHSOp, RHSOp); if (FoldOp.getOpcode() != ISD::UNDEF && diff --git a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll index f2288c3..89c9037 100644 --- a/test/CodeGen/ARM/2009-11-02-NegativeLane.ll +++ b/test/CodeGen/ARM/2009-11-02-NegativeLane.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.32 +; RUN: llc -mcpu=cortex-a8 < %s | grep vdup.16 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" @@ -7,12 +7,12 @@ entry: br i1 undef, label %return, label %bb bb: ; preds = %bb, %entry - %0 = load float* undef, align 4 ; <float> [#uses=1] - %1 = insertelement <4 x float> undef, float %0, i32 2 ; <<4 x float>> [#uses=1] - %2 = insertelement <4 x float> %1, float undef, i32 3 ; <<4 x float>> [#uses=1] - %3 = fmul <4 x float> undef, %2 ; <<4 x float>> [#uses=1] - %4 = extractelement <4 x float> %3, i32 1 ; <float> [#uses=1] - store float %4, float* undef, align 4 + %0 = load i16* undef, align 2 + %1 = insertelement <8 x i16> undef, i16 %0, i32 2 + %2 = insertelement <8 x i16> %1, i16 undef, i32 3 + %3 = mul <8 x i16> %2, %2 + %4 = extractelement <8 x i16> %3, i32 2 + store i16 %4, i16* undef, align 2 br i1 undef, label %return, label %bb return: ; preds = %bb, %entry |