diff options
| -rw-r--r-- | lib/Target/Mips/MipsISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 3 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.h | 4 | ||||
| -rw-r--r-- | test/CodeGen/Mips/2010-11-09-Mul.ll | 15 |
4 files changed, 21 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index b4fd49d..ff9f12e 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -386,6 +386,8 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) { /// Special Muls case ISD::MUL: + if (Subtarget.isMips32()) + break; case ISD::MULHS: case ISD::MULHU: { SDValue MulOp1 = Node->getOperand(0); diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 61f51e7..50ce760 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -62,6 +62,7 @@ def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">; def HasBitCount : Predicate<"Subtarget.hasBitCount()">; def HasSwap : Predicate<"Subtarget.hasSwap()">; def HasCondMov : Predicate<"Subtarget.hasCondMov()">; +def IsMips32 : Predicate<"Subtarget.isMips32()">; //===----------------------------------------------------------------------===// // Mips Operand, Complex Patterns and Transformations Definitions. @@ -487,7 +488,7 @@ def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">; // MUL is a assembly macro in the current used ISAs. In recent ISA's // it is a real instruction. -//def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>; +def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 3d13f82..e4f4b33 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -31,7 +31,7 @@ public: protected: enum MipsArchEnum { - Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2, Mips64, Mips64r2 + Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2 }; // Mips architecture version @@ -100,7 +100,7 @@ public: const std::string &CPU); bool isMips1() const { return MipsArchVersion == Mips1; } - bool isMips32() const { return MipsArchVersion == Mips32; } + bool isMips32() const { return MipsArchVersion >= Mips32; } bool isMips32r2() const { return MipsArchVersion == Mips32r2; } bool isLittle() const { return IsLittle; } diff --git a/test/CodeGen/Mips/2010-11-09-Mul.ll b/test/CodeGen/Mips/2010-11-09-Mul.ll new file mode 100644 index 0000000..65a10b5 --- /dev/null +++ b/test/CodeGen/Mips/2010-11-09-Mul.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +; CHECK: mul $2, $5, $4 +define i32 @mul1(i32 %a, i32 %b) nounwind readnone { +entry: + %mul = mul i32 %b, %a + ret i32 %mul +} + +; CHECK: mul $2, $5, $4 +define i32 @mul2(i32 %a, i32 %b) nounwind readnone { +entry: + %mul = mul nsw i32 %b, %a + ret i32 %mul +} |