diff options
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.h | 24 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 24 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 2 |
3 files changed, 24 insertions, 26 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index 21b174d..054ea24 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -123,18 +123,18 @@ namespace ARMII { NGetLnFrm = 26 << FormShift, NSetLnFrm = 27 << FormShift, NDupFrm = 28 << FormShift, - NLdStFrm = 31 << FormShift, - N1RegModImmFrm= 32 << FormShift, - N2RegFrm = 33 << FormShift, - NVCVTFrm = 34 << FormShift, - NVDupLnFrm = 35 << FormShift, - N2RegVShLFrm = 36 << FormShift, - N2RegVShRFrm = 37 << FormShift, - N3RegFrm = 38 << FormShift, - N3RegVShFrm = 39 << FormShift, - NVExtFrm = 40 << FormShift, - NVMulSLFrm = 41 << FormShift, - NVTBLFrm = 42 << FormShift, + NLdStFrm = 29 << FormShift, + N1RegModImmFrm= 30 << FormShift, + N2RegFrm = 31 << FormShift, + NVCVTFrm = 32 << FormShift, + NVDupLnFrm = 33 << FormShift, + N2RegVShLFrm = 34 << FormShift, + N2RegVShRFrm = 35 << FormShift, + N3RegFrm = 36 << FormShift, + N3RegVShFrm = 37 << FormShift, + NVExtFrm = 38 << FormShift, + NVMulSLFrm = 39 << FormShift, + NVTBLFrm = 40 << FormShift, //===------------------------------------------------------------------===// // Misc flags. diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index b453234..ac568e7 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -55,18 +55,18 @@ def MiscFrm : Format<25>; def NGetLnFrm : Format<26>; def NSetLnFrm : Format<27>; def NDupFrm : Format<28>; -def NLdStFrm : Format<31>; -def N1RegModImmFrm: Format<32>; -def N2RegFrm : Format<33>; -def NVCVTFrm : Format<34>; -def NVDupLnFrm : Format<35>; -def N2RegVShLFrm : Format<36>; -def N2RegVShRFrm : Format<37>; -def N3RegFrm : Format<38>; -def N3RegVShFrm : Format<39>; -def NVExtFrm : Format<40>; -def NVMulSLFrm : Format<41>; -def NVTBLFrm : Format<42>; +def NLdStFrm : Format<29>; +def N1RegModImmFrm: Format<30>; +def N2RegFrm : Format<31>; +def NVCVTFrm : Format<32>; +def NVDupLnFrm : Format<33>; +def N2RegVShLFrm : Format<34>; +def N2RegVShRFrm : Format<35>; +def N3RegFrm : Format<36>; +def N3RegVShFrm : Format<37>; +def NVExtFrm : Format<38>; +def NVMulSLFrm : Format<39>; +def NVTBLFrm : Format<40>; // Misc flags. diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 65413fa..7eccead 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -3089,8 +3089,6 @@ static const DisassembleFP FuncPtrs[] = { &DisassembleNGetLnFrm, &DisassembleNSetLnFrm, &DisassembleNDupFrm, - 0, - 0, // VLD and VST (including one lane) Instructions. &DisassembleNLdSt, |