aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--lib/Target/ARM/ARMInstrThumb2.td45
-rw-r--r--lib/Target/ARM/ARMMCCodeEmitter.cpp15
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassembler.cpp35
-rw-r--r--lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h9
-rw-r--r--utils/TableGen/EDEmitter.cpp2
5 files changed, 16 insertions, 90 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 9f0399a..1066660 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -127,7 +127,7 @@ def imm0_255_not : PatLeaf<(i32 imm), [{
def t2addrmode_imm12 : Operand<i32>,
ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
let PrintMethod = "printAddrModeImm12Operand";
- string EncoderMethod = "getT2AddrModeImm12OpValue";
+ string EncoderMethod = "getAddrModeImm12OpValue";
let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
}
@@ -146,11 +146,6 @@ def t2am_imm8_offset : Operand<i32>,
string EncoderMethod = "getT2AddrModeImm8OffsetOpValue";
}
-def t2am_imm12_offset : Operand<i32> {
- string EncoderMethod = "getT2AddrModeImm12OffsetOpValue";
-}
-
-
// t2addrmode_imm8s4 := reg +/- (imm8 << 2)
def t2addrmode_imm8s4 : Operand<i32> {
let PrintMethod = "printT2AddrModeImm8s4Operand";
@@ -845,9 +840,10 @@ multiclass T2I_ld<bit signed, bits<2> opcod, string opc,
bits<4> Rt;
let Inst{15-12} = Rt{3-0};
- bits<16> addr;
- let Inst{19-16} = addr{15-12}; // Rn
- let Inst{11-0} = addr{11-0}; // imm
+ bits<17> addr;
+ let Inst{19-16} = addr{16-13}; // Rn
+ let Inst{23} = addr{12}; // U
+ let Inst{11-0} = addr{11-0}; // imm
}
def i8 : T2Ii8 <(outs GPR:$Rt), (ins t2addrmode_imm8:$addr), iii,
opc, "\t$Rt, $addr",
@@ -925,9 +921,10 @@ multiclass T2I_st<bits<2> opcod, string opc,
bits<4> Rt;
let Inst{15-12} = Rt{3-0};
- bits<16> addr;
- let Inst{19-16} = addr{15-12}; // Rn
- let Inst{11-0} = addr{11-0}; // imm
+ bits<17> addr;
+ let Inst{19-16} = addr{16-13}; // Rn
+ let Inst{23} = addr{12}; // U
+ let Inst{11-0} = addr{11-0}; // imm
}
def i8 : T2Ii8 <(outs), (ins GPR:$Rt, t2addrmode_imm8:$addr), iii,
opc, "\t$Rt, $addr",
@@ -1539,14 +1536,14 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
[(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> {
let Inst{31-25} = 0b1111100;
let Inst{24} = instr;
- let Inst{23} = 1; // U = 1
let Inst{22} = 0;
let Inst{21} = write;
let Inst{20} = 1;
let Inst{15-12} = 0b1111;
- bits<16> addr;
- let Inst{19-16} = addr{15-12}; // Rn
+ bits<17> addr;
+ let Inst{19-16} = addr{16-13}; // Rn
+ let Inst{23} = addr{12}; // U
let Inst{11-0} = addr{11-0}; // imm12
}
@@ -1584,24 +1581,6 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let Inst{3-0} = addr{5-2}; // Rm
let Inst{5-4} = addr{1-0}; // imm2
}
-
- let isCodeGenOnly = 1 in
- def pci : T2Ipc<(outs), (ins t2am_imm12_offset:$addr), IIC_Preload, opc,
- "\t$addr",
- []> {
- let Inst{31-25} = 0b1111100;
- let Inst{24} = write;
- let Inst{23} = ?; // add = (U == 1)
- let Inst{22} = 0;
- let Inst{21} = instr;
- let Inst{20} = 1;
- let Inst{19-16} = 0b1111; // Rn = 0b1111
- let Inst{15-12} = 0b1111;
-
- bits<13> addr;
- let Inst{23} = addr{12};
- let Inst{11-0} = addr{11-0};
- }
}
defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index fd595fd..0a506d5 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -185,8 +185,6 @@ public:
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
SmallVectorImpl<MCFixup> &Fixups) const;
- unsigned getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups) const;
/// getSORegOpValue - Return an encoded so_reg shifted register value.
unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
@@ -746,19 +744,6 @@ getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
}
unsigned ARMMCCodeEmitter::
-getT2AddrModeImm12OpValue(const MCInst &MI, unsigned OpNum,
- SmallVectorImpl<MCFixup> &Fixups) const {
- const MCOperand &MO1 = MI.getOperand(OpNum);
- const MCOperand &MO2 = MI.getOperand(OpNum+1);
-
- // FIXME: Needs fixup support.
- unsigned Value = getARMRegisterNumbering(MO1.getReg());
- Value <<= 12;
- Value |= MO2.getImm() & 4095;
- return Value;
-}
-
-unsigned ARMMCCodeEmitter::
getT2SORegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
// Sub-operands are [reg, imm]. The first register is Rm, the reg to be
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index abdcf81..d4aa03c 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -350,36 +350,6 @@ static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned &insn) {
return decodeThumbInstruction(insn);
}
-static inline bool Thumb2PreloadOpcodeNoPCI(unsigned Opcode) {
- switch (Opcode) {
- default:
- return false;
- case ARM::t2PLDi12: case ARM::t2PLDi8:
- case ARM::t2PLDs:
- case ARM::t2PLDWi12: case ARM::t2PLDWi8:
- case ARM::t2PLDWs:
- case ARM::t2PLIi12: case ARM::t2PLIi8:
- case ARM::t2PLIs:
- return true;
- }
-}
-
-static inline unsigned T2Morph2Preload2PCI(unsigned Opcode) {
- switch (Opcode) {
- default:
- return 0;
- case ARM::t2PLDi12: case ARM::t2PLDi8:
- case ARM::t2PLDs:
- return ARM::t2PLDpci;
- case ARM::t2PLDWi12: case ARM::t2PLDWi8:
- case ARM::t2PLDWs:
- return ARM::t2PLDWpci;
- case ARM::t2PLIi12: case ARM::t2PLIi8:
- case ARM::t2PLIs:
- return ARM::t2PLIpci;
- }
-}
-
//
// Public interface for the disassembler
//
@@ -486,11 +456,6 @@ bool ThumbDisassembler::getInstruction(MCInst &MI,
// instructions as well.
unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
- // A8.6.117/119/120/121.
- // PLD/PLDW/PLI instructions with Rn==15 is transformed to the pci variant.
- if (Thumb2PreloadOpcodeNoPCI(Opcode) && slice(insn, 19, 16) == 15)
- Opcode = T2Morph2Preload2PCI(Opcode);
-
ARMFormat Format = ARMFormats[Opcode];
Size = IsThumb2 ? 4 : 2;
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index eb92085..2c8345c 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -1711,11 +1711,11 @@ static inline bool Thumb2PreloadOpcode(unsigned Opcode) {
switch (Opcode) {
default:
return false;
- case ARM::t2PLDi12: case ARM::t2PLDi8: case ARM::t2PLDpci:
+ case ARM::t2PLDi12: case ARM::t2PLDi8:
case ARM::t2PLDs:
- case ARM::t2PLDWi12: case ARM::t2PLDWi8: case ARM::t2PLDWpci:
+ case ARM::t2PLDWi12: case ARM::t2PLDWi8:
case ARM::t2PLDWs:
- case ARM::t2PLIi12: case ARM::t2PLIi8: case ARM::t2PLIpci:
+ case ARM::t2PLIi12: case ARM::t2PLIi8:
case ARM::t2PLIs:
return true;
}
@@ -1752,8 +1752,7 @@ static bool DisassembleThumb2PreLoad(MCInst &MI, unsigned Opcode, uint32_t insn,
&& !OpInfo[OpIdx].isOptionalDef()
&& "Pure imm operand expected");
int Offset = 0;
- if (Opcode == ARM::t2PLDpci || Opcode == ARM::t2PLDWpci ||
- Opcode == ARM::t2PLIpci) {
+ if (slice(insn, 19, 16) == 0xFF) {
bool Negative = slice(insn, 23, 23) == 0;
unsigned Imm12 = getImm12(insn);
Offset = Negative ? -1 - Imm12 : 1 * Imm12;
diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp
index fcce3a5..61d4ccd 100644
--- a/utils/TableGen/EDEmitter.cpp
+++ b/utils/TableGen/EDEmitter.cpp
@@ -614,7 +614,6 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
MISC("it_mask", "kOperandTypeThumbITMask"); // I
MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I
MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
- MISC("t2am_imm12_offset", "kOperandTypeThumb2AddrModeImm12Offset");//I
MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I
MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I
MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I
@@ -841,7 +840,6 @@ static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
operandTypes.addEntry("kOperandTypeThumb2SoImm");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
- operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12Offset");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
generated by cgit v1.1 at 2025-07-03 02:06:00 +0000