diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/X86/setcc-narrowing.ll | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f2199d7..3881b0e 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1185,6 +1185,7 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, // the test is for equality or unsigned, and all 1 bits of the const are // in the same partial word, see if we can shorten the load. if (DCI.isBeforeLegalize() && + !ISD::isSignedIntSetCC(Cond) && N0.getOpcode() == ISD::AND && C1 == 0 && N0.getNode()->hasOneUse() && isa<LoadSDNode>(N0.getOperand(0)) && diff --git a/test/CodeGen/X86/setcc-narrowing.ll b/test/CodeGen/X86/setcc-narrowing.ll new file mode 100644 index 0000000..25cb2c8 --- /dev/null +++ b/test/CodeGen/X86/setcc-narrowing.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=i686-apple-darwin | FileCheck %s +; PR17338 + +@t1.global = internal global i64 -1, align 8 + +define i32 @t1() nounwind ssp { +entry: +; CHECK-LABEL: t1: +; CHECK: cmpl $0, _t1.global +; CHECK-NEXT: setne %al +; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: ret + %0 = load i64* @t1.global, align 8 + %and = and i64 4294967295, %0 + %cmp = icmp sgt i64 %and, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} |