diff options
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAG.h | 29 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 40 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 40 | ||||
| -rw-r--r-- | lib/Target/Alpha/AlphaISelLowering.cpp | 19 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 48 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 30 |
6 files changed, 73 insertions, 133 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index d62c1b7..1a24296 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -319,7 +319,6 @@ public: SDValue getRegister(unsigned Reg, MVT VT); SDValue getDbgStopPoint(SDValue Root, unsigned Line, unsigned Col, Value *CU); -// SDValue getLabel(unsigned Opcode, SDValue Root, unsigned LabelID); SDValue getLabel(unsigned Opcode, DebugLoc dl, SDValue Root, unsigned LabelID); @@ -393,8 +392,6 @@ public: /// Returns the ConvertRndSat Note: Avoid using this node because it may /// disappear in the future and most targets don't support it. -// SDValue getConvertRndSat(MVT VT, SDValue Val, SDValue DTy, SDValue STy, -// SDValue Rnd, SDValue Sat, ISD::CvtCode Code); SDValue getConvertRndSat(MVT VT, DebugLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code); @@ -512,11 +509,6 @@ public: /// getSetCC - Helper function to make it easier to build SetCC's if you just /// have an ISD::CondCode instead of an SDValue. /// - SDValue getSetCC(MVT VT, SDValue LHS, SDValue RHS, - ISD::CondCode Cond) { - return getNode(ISD::SETCC, DebugLoc::getUnknownLoc(), VT, - LHS, RHS, getCondCode(Cond)); - } SDValue getSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) { return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond)); @@ -525,11 +517,6 @@ public: /// getVSetCC - Helper function to make it easier to build VSetCC's nodes /// if you just have an ISD::CondCode instead of an SDValue. /// - SDValue getVSetCC(MVT VT, SDValue LHS, SDValue RHS, - ISD::CondCode Cond) { - return getNode(ISD::VSETCC, DebugLoc::getUnknownLoc(), VT, - LHS, RHS, getCondCode(Cond)); - } SDValue getVSetCC(DebugLoc DL, MVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond) { return getNode(ISD::VSETCC, DL, VT, LHS, RHS, getCondCode(Cond)); @@ -538,11 +525,6 @@ public: /// getSelectCC - Helper function to make it easier to build SelectCC's if you /// just have an ISD::CondCode instead of an SDValue. /// - SDValue getSelectCC(SDValue LHS, SDValue RHS, - SDValue True, SDValue False, ISD::CondCode Cond) { - return getNode(ISD::SELECT_CC, DebugLoc::getUnknownLoc(), True.getValueType(), - LHS, RHS, True, False, getCondCode(Cond)); - } SDValue getSelectCC(DebugLoc DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond) { return getNode(ISD::SELECT_CC, DL, True.getValueType(), @@ -568,12 +550,6 @@ public: /// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a /// result and takes a list of operands. - SDValue getMemIntrinsicNode(unsigned Opcode, - const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align = 0, bool Vol = false, - bool ReadMem = true, bool WriteMem = true); SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, @@ -581,11 +557,6 @@ public: unsigned Align = 0, bool Vol = false, bool ReadMem = true, bool WriteMem = true); - SDValue getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align = 0, bool Vol = false, - bool ReadMem = true, bool WriteMem = true); SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, MVT MemVT, const Value *srcValue, int SVOff, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 59ce6b7..fa32aab 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3489,18 +3489,6 @@ SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, } SDValue -SelectionDAG::getMemIntrinsicNode(unsigned Opcode, - const MVT *VTs, unsigned NumVTs, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align, bool Vol, - bool ReadMem, bool WriteMem) { - return getMemIntrinsicNode(Opcode, makeVTList(VTs, NumVTs), Ops, NumOps, - MemVT, srcValue, SVOff, Align, Vol, - ReadMem, WriteMem); -} - -SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const MVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, @@ -3513,34 +3501,6 @@ SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, } SDValue -SelectionDAG::getMemIntrinsicNode(unsigned Opcode, SDVTList VTList, - const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, - unsigned Align, bool Vol, - bool ReadMem, bool WriteMem) { - // Memoize the node unless it returns a flag. - MemIntrinsicSDNode *N; - if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { - FoldingSetNodeID ID; - AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); - void *IP = 0; - if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) - return SDValue(E, 0); - - N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); - new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, - srcValue, SVOff, Align, Vol, ReadMem, WriteMem); - CSEMap.InsertNode(N, IP); - } else { - N = NodeAllocator.Allocate<MemIntrinsicSDNode>(); - new (N) MemIntrinsicSDNode(Opcode, VTList, Ops, NumOps, MemVT, - srcValue, SVOff, Align, Vol, ReadMem, WriteMem); - } - AllNodes.push_back(N); - return SDValue(N, 0); -} - -SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, MVT MemVT, const Value *srcValue, int SVOff, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index a235a11..c3cff20 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -1318,6 +1318,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { SDValue Cond; SDValue CondLHS = getValue(CB.CmpLHS); + DebugLoc dl = getCurDebugLoc(); // Build the setcc now. if (CB.CmpMHS == NULL) { @@ -1327,10 +1328,9 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { Cond = CondLHS; else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { SDValue True = DAG.getConstant(1, CondLHS.getValueType()); - Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), - CondLHS.getValueType(), CondLHS, True); + Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); } else - Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); + Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); } else { assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); @@ -1341,11 +1341,12 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { MVT VT = CmpOp.getValueType(); if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { - Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); + Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), + ISD::SETLE); } else { - SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), + SDValue SUB = DAG.getNode(ISD::SUB, dl, VT, CmpOp, DAG.getConstant(Low, VT)); - Cond = DAG.getSetCC(MVT::i1, SUB, + Cond = DAG.getSetCC(dl, MVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); } } @@ -1366,10 +1367,9 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { if (CB.TrueBB == NextBlock) { std::swap(CB.TrueBB, CB.FalseBB); SDValue True = DAG.getConstant(1, Cond.getValueType()); - Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), - Cond.getValueType(), Cond, True); + Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); } - SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), + SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, MVT::Other, getControlRoot(), Cond, DAG.getBasicBlock(CB.TrueBB)); @@ -1385,7 +1385,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { if (CB.FalseBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); } } @@ -1435,7 +1435,8 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, // Emit the range check for the jump table, and branch to the default block // for the switch statement if the value being switched on exceeds the largest // case in the switch. - SDValue CMP = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB, + SDValue CMP = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), SUB, DAG.getConstant(JTH.Last-JTH.First,VT), ISD::SETUGT); @@ -1467,8 +1468,9 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { DAG.getConstant(B.First, VT)); // Check range - SDValue RangeCmp = DAG.getSetCC(TLI.getSetCCResultType(SUB.getValueType()), SUB, - DAG.getConstant(B.Range, VT), + SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(SUB.getValueType()), + SUB, DAG.getConstant(B.Range, VT), ISD::SETUGT); SDValue ShiftOp; @@ -1522,7 +1524,8 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), TLI.getPointerTy(), SwitchVal, DAG.getConstant(B.Mask, TLI.getPointerTy())); - SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()), + SDValue AndCmp = DAG.getSetCC(getCurDebugLoc(), + TLI.getSetCCResultType(AndOp.getValueType()), AndOp, DAG.getConstant(0, TLI.getPointerTy()), ISD::SETNE); @@ -2191,7 +2194,7 @@ void SelectionDAGLowering::visitICmp(User &I) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(),MVT::i1, Op1, Op2, Opcode)); } void SelectionDAGLowering::visitFCmp(User &I) { @@ -2203,7 +2206,7 @@ void SelectionDAGLowering::visitFCmp(User &I) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Condition = getFCmpCondCode(predicate); - setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition)); + setValue(&I, DAG.getSetCC(getCurDebugLoc(), MVT::i1, Op1, Op2, Condition)); } void SelectionDAGLowering::visitVICmp(User &I) { @@ -2215,7 +2218,8 @@ void SelectionDAGLowering::visitVICmp(User &I) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - setValue(&I, DAG.getVSetCC(Op1.getValueType(), Op1, Op2, Opcode)); + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), Op1.getValueType(), + Op1, Op2, Opcode)); } void SelectionDAGLowering::visitVFCmp(User &I) { @@ -2229,7 +2233,7 @@ void SelectionDAGLowering::visitVFCmp(User &I) { ISD::CondCode Condition = getFCmpCondCode(predicate); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getVSetCC(DestVT, Op1, Op2, Condition)); + setValue(&I, DAG.getVSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); } void SelectionDAGLowering::visitSelect(User &I) { diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index 753906e..4346a3f 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -434,26 +434,27 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, Chain = N->getOperand(0); SDValue VAListP = N->getOperand(1); const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); + DebugLoc dl = N->getDebugLoc(); - SDValue Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS, 0); - SDValue Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP, + SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0); + SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP, DAG.getConstant(8, MVT::i64)); - SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1), + SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1), Tmp, NULL, 0, MVT::i32); - DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset); + DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset); if (N->getValueType(0).isFloatingPoint()) { //if fp && Offset < 6*8, then subtract 6*8 from DataPtr - SDValue FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr, + SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr, DAG.getConstant(8*6, MVT::i64)); - SDValue CC = DAG.getSetCC(MVT::i64, Offset, + SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset, DAG.getConstant(8*6, MVT::i64), ISD::SETLT); - DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr); + DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr); } - SDValue NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset, + SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset, DAG.getConstant(8, MVT::i64)); - Chain = DAG.getTruncStore(Offset.getValue(1), NewOffset, Tmp, NULL, 0, + Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0, MVT::i32); } diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 0718330..9e48962 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -2455,6 +2455,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) { CondCodeSDNode *CC = dyn_cast<CondCodeSDNode>(Op.getOperand(2)); + DebugLoc dl = Op.getNode()->getDebugLoc(); assert(CC != 0 && "LowerSETCC: CondCodeSDNode should not be null here!\n"); SDValue lhs = Op.getOperand(0); @@ -2468,35 +2469,35 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently // selected to a NOP: - SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, lhs); + SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs); SDValue lhsHi32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, - DAG.getNode(ISD::SRL, IntVT, + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::SRL, dl, IntVT, i64lhs, DAG.getConstant(32, MVT::i32))); SDValue lhsHi32abs = - DAG.getNode(ISD::AND, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32)); SDValue lhsLo32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, i64lhs); + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs); // SETO and SETUO only use the lhs operand: if (CC->get() == ISD::SETO) { // Evaluates to true if Op0 is not [SQ]NaN - lowers to the inverse of // SETUO APInt ccResultAllOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits()); - return DAG.getNode(ISD::XOR, ccResultVT, - DAG.getSetCC(ccResultVT, + return DAG.getNode(ISD::XOR, dl, ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhs, DAG.getConstantFP(0.0, lhsVT), ISD::SETUO), DAG.getConstant(ccResultAllOnes, ccResultVT)); } else if (CC->get() == ISD::SETUO) { // Evaluates to true if Op0 is [SQ]NaN - return DAG.getNode(ISD::AND, ccResultVT, - DAG.getSetCC(ccResultVT, + return DAG.getNode(ISD::AND, dl, ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhsHi32abs, DAG.getConstant(0x7ff00000, MVT::i32), ISD::SETGE), - DAG.getSetCC(ccResultVT, + DAG.getSetCC(dl, ccResultVT, lhsLo32, DAG.getConstant(0, MVT::i32), ISD::SETGT)); @@ -2504,26 +2505,26 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, IntVT, rhs); SDValue rhsHi32 = - DAG.getNode(ISD::TRUNCATE, MVT::i32, - DAG.getNode(ISD::SRL, IntVT, + DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::SRL, dl, IntVT, i64rhs, DAG.getConstant(32, MVT::i32))); // If a value is negative, subtract from the sign magnitude constant: SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT); // Convert the sign-magnitude representation into 2's complement: - SDValue lhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT, + SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, lhsHi32, DAG.getConstant(31, MVT::i32)); - SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64lhs); + SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs); SDValue lhsSelect = - DAG.getNode(ISD::SELECT, IntVT, + DAG.getNode(ISD::SELECT, dl, IntVT, lhsSelectMask, lhsSignMag2TC, i64lhs); - SDValue rhsSelectMask = DAG.getNode(ISD::SRA, ccResultVT, + SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, rhsHi32, DAG.getConstant(31, MVT::i32)); - SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, IntVT, signMag2TC, i64rhs); + SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs); SDValue rhsSelect = - DAG.getNode(ISD::SELECT, IntVT, + DAG.getNode(ISD::SELECT, dl, IntVT, rhsSelectMask, rhsSignMag2TC, i64rhs); unsigned compareOp; @@ -2554,19 +2555,20 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, } SDValue result = - DAG.getSetCC(ccResultVT, lhsSelect, rhsSelect, (ISD::CondCode) compareOp); + DAG.getSetCC(dl, ccResultVT, lhsSelect, rhsSelect, + (ISD::CondCode) compareOp); if ((CC->get() & 0x8) == 0) { // Ordered comparison: - SDValue lhsNaN = DAG.getSetCC(ccResultVT, + SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT, lhs, DAG.getConstantFP(0.0, MVT::f64), ISD::SETO); - SDValue rhsNaN = DAG.getSetCC(ccResultVT, + SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT, rhs, DAG.getConstantFP(0.0, MVT::f64), ISD::SETO); - SDValue ordered = DAG.getNode(ISD::AND, ccResultVT, lhsNaN, rhsNaN); + SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN); - result = DAG.getNode(ISD::AND, ccResultVT, ordered, result); + result = DAG.getNode(ISD::AND, dl, ccResultVT, ordered, result); } return result; diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 6d324cc..da567f7 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1173,6 +1173,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); + DebugLoc dl = Op.getNode()->getDebugLoc(); // If we're comparing for equality to zero, expose the fact that this is // implented as a ctlz/srl pair on ppc, so that the dag combiner can @@ -1183,13 +1184,13 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { SDValue Zext = Op.getOperand(0); if (VT.bitsLT(MVT::i32)) { VT = MVT::i32; - Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0)); + Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); } unsigned Log2b = Log2_32(VT.getSizeInBits()); - SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext); - SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz, + SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); + SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, DAG.getConstant(Log2b, MVT::i32)); - return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc); + return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); } // Leave comparisons against 0 and -1 alone for now, since they're usually // optimized. FIXME: revisit this when we can custom lower all setcc @@ -1206,9 +1207,9 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { MVT LHSVT = Op.getOperand(0).getValueType(); if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { MVT VT = Op.getValueType(); - SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0), + SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), Op.getOperand(1)); - return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC); + return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); } return SDValue(); } @@ -3035,6 +3036,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { } SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getNode()->getDebugLoc(); MVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && @@ -3047,16 +3049,16 @@ SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue Amt = Op.getOperand(2); MVT AmtVT = Amt.getValueType(); - SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT, + SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); - SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt); - SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3); - SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt, + SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt); + SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); + SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); + SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, AmtVT)); - SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5); - SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt); - SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT), + SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); + SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); + SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT), Tmp4, Tmp6, ISD::SETLE); SDValue OutOps[] = { OutLo, OutHi }; return DAG.getMergeValues(OutOps, 2); |