diff options
-rw-r--r-- | lib/Target/ARM/ARM.td | 7 | ||||
-rw-r--r-- | lib/Target/ARM/ARMSubtarget.cpp | 1 | ||||
-rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 5 | ||||
-rw-r--r-- | lib/Target/ARM/ARMTargetMachine.cpp | 3 | ||||
-rw-r--r-- | test/CodeGen/ARM/div.ll | 10 | ||||
-rw-r--r-- | test/CodeGen/Thumb2/div.ll | 2 |
6 files changed, 15 insertions, 13 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 5da83a6..b9310bb 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -28,6 +28,8 @@ def FeatureNEON : SubtargetFeature<"neon", "ARMFPUType", "NEON", "Enable NEON instructions">; def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2", "Enable Thumb2 instructions">; +def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", + "Does not support ARM mode execution">; def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", "Enable half-precision floating point">; def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true", @@ -69,7 +71,7 @@ def ArchV6 : SubtargetFeature<"v6", "ARMArchVersion", "V6", "ARM v6">; def ArchV6M : SubtargetFeature<"v6m", "ARMArchVersion", "V6M", "ARM v6m", - [FeatureDB]>; + [FeatureNoARM, FeatureDB]>; def ArchV6T2 : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2", "ARM v6t2", [FeatureThumb2]>; @@ -78,7 +80,8 @@ def ArchV7A : SubtargetFeature<"v7a", "ARMArchVersion", "V7A", [FeatureThumb2, FeatureNEON, FeatureDB]>; def ArchV7M : SubtargetFeature<"v7m", "ARMArchVersion", "V7M", "ARM v7M", - [FeatureThumb2, FeatureDB, FeatureHWDiv]>; + [FeatureThumb2, FeatureNoARM, FeatureDB, + FeatureHWDiv]>; //===----------------------------------------------------------------------===// // ARM Processors supported. diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index db50c9f..b4eb83e 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -36,6 +36,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, , SlowFPBrcc(false) , IsThumb(isT) , ThumbMode(Thumb1) + , NoARM(false) , PostRAScheduler(false) , IsR9Reserved(ReserveR9) , UseMovt(UseMOVT) diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index c5b3402..ad9fc11 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -63,6 +63,9 @@ protected: /// ThumbMode - Indicates supported Thumb version. ThumbTypeEnum ThumbMode; + /// NoARM - True if subtarget does not support ARM mode execution. + bool NoARM; + /// PostRAScheduler - True if using post-register-allocation scheduler. bool PostRAScheduler; @@ -136,6 +139,8 @@ protected: bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } bool hasV7Ops() const { return ARMArchVersion >= V7A; } + bool hasARMOps() const { return !NoARM; } + bool hasVFP2() const { return ARMFPUType >= VFPv2; } bool hasVFP3() const { return ARMFPUType >= VFPv3; } bool hasNEON() const { return ARMFPUType >= NEON; } diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index ac9b6bf..30ff827 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -65,6 +65,9 @@ ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, "v128:64:128-v64:64:64-n32")), TLInfo(*this), TSInfo(*this) { + if (!Subtarget.hasARMOps()) + report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " + "support ARM mode execution!"); } ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index d833afa..448b437 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,13 +1,9 @@ ; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECK-ARM -; RUN: llc < %s -march=arm -mcpu=cortex-m3 \ -; RUN: | FileCheck %s -check-prefix=CHECK-ARMV7M define i32 @f1(i32 %a, i32 %b) { entry: ; CHECK-ARM: f1 ; CHECK-ARM: __divsi3 -; CHECK-ARMV7M: f1 -; CHECK-ARMV7M: sdiv %tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -16,8 +12,6 @@ define i32 @f2(i32 %a, i32 %b) { entry: ; CHECK-ARM: f2 ; CHECK-ARM: __udivsi3 -; CHECK-ARMV7M: f2 -; CHECK-ARMV7M: udiv %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -26,8 +20,6 @@ define i32 @f3(i32 %a, i32 %b) { entry: ; CHECK-ARM: f3 ; CHECK-ARM: __modsi3 -; CHECK-ARMV7M: f3 -; CHECK-ARMV7M: sdiv %tmp1 = srem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } @@ -36,8 +28,6 @@ define i32 @f4(i32 %a, i32 %b) { entry: ; CHECK-ARM: f4 ; CHECK-ARM: __umodsi3 -; CHECK-ARMV7M: f4 -; CHECK-ARMV7M: udiv %tmp1 = urem i32 %a, %b ; <i32> [#uses=1] ret i32 %tmp1 } diff --git a/test/CodeGen/Thumb2/div.ll b/test/CodeGen/Thumb2/div.ll index 0cddd48..e63a115 100644 --- a/test/CodeGen/Thumb2/div.ll +++ b/test/CodeGen/Thumb2/div.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 \ ; RUN: | FileCheck %s -check-prefix=CHECK-THUMB -; RUN: llc < %s -march=arm -mcpu=cortex-m3 -mattr=+thumb2 \ +; RUN: llc < %s -march=thumb -mcpu=cortex-m3 -mattr=+thumb2 \ ; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M define i32 @f1(i32 %a, i32 %b) { |