diff options
| -rw-r--r-- | include/llvm/IntrinsicsX86.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/X86/vec_shift.ll | 34 |
3 files changed, 38 insertions, 4 deletions
diff --git a/include/llvm/IntrinsicsX86.td b/include/llvm/IntrinsicsX86.td index 5405902..28a4472 100644 --- a/include/llvm/IntrinsicsX86.td +++ b/include/llvm/IntrinsicsX86.td @@ -329,13 +329,13 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.". llvm_i32_ty], [IntrNoMem]>; def int_x86_sse2_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw128">, Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, - llvm_v4i32_ty], [IntrNoMem]>; + llvm_v8i16_ty], [IntrNoMem]>; def int_x86_sse2_psrl_d : GCCBuiltin<"__builtin_ia32_psrld128">, Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; def int_x86_sse2_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq128">, Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, - llvm_v4i32_ty], [IntrNoMem]>; + llvm_v2i64_ty], [IntrNoMem]>; def int_x86_sse2_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi128">, Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>; diff --git a/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll b/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll index 33ff755..64ccef3 100644 --- a/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll +++ b/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll @@ -3,7 +3,7 @@ declare <8 x i16> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) -declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <4 x i32>) +declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) define fastcc void @test(i32* %src, i32 %sbpr, i32* %dst, i32 %dbpr, i32 %w, i32 %h, i32 %dstalpha, i32 %mask) { %tmp633 = shufflevector <8 x i16> zeroinitializer, <8 x i16> undef, <8 x i32> < i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7 > @@ -12,7 +12,7 @@ define fastcc void @test(i32* %src, i32 %sbpr, i32* %dst, i32 %dbpr, i32 %w, i32 %tmp777 = add <4 x i32> %tmp776, shufflevector (<4 x i32> < i32 65537, i32 0, i32 0, i32 0 >, <4 x i32> < i32 65537, i32 0, i32 0, i32 0 >, <4 x i32> zeroinitializer) %tmp805 = add <4 x i32> %tmp777, zeroinitializer %tmp832 = bitcast <4 x i32> %tmp805 to <8 x i16> - %tmp838 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp832, <4 x i32> < i32 8, i32 undef, i32 undef, i32 undef > ) + %tmp838 = tail call <8 x i16> @llvm.x86.sse2.psrl.w( <8 x i16> %tmp832, <8 x i16> < i16 8, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef > ) %tmp1020 = tail call <8 x i16> @llvm.x86.sse2.packuswb.128( <8 x i16> zeroinitializer, <8 x i16> %tmp838 ) %tmp1030 = bitcast <8 x i16> %tmp1020 to <4 x i32> %tmp1033 = add <4 x i32> zeroinitializer, %tmp1030 diff --git a/test/CodeGen/X86/vec_shift.ll b/test/CodeGen/X86/vec_shift.ll new file mode 100644 index 0000000..9c595bc --- /dev/null +++ b/test/CodeGen/X86/vec_shift.ll @@ -0,0 +1,34 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psllw +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psrlq +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep psraw + +define <2 x i64> @t1(<2 x i64> %b1, <2 x i64> %c) nounwind { +entry: + %tmp6 = bitcast <2 x i64> %c to <8 x i16> ; <<8 x i16>> [#uses=1] + %tmp8 = bitcast <2 x i64> %b1 to <8 x i16> ; <<8 x i16>> [#uses=1] + %tmp9 = tail call <8 x i16> @llvm.x86.sse2.psll.w( <8 x i16> %tmp8, <8 x i16> %tmp6 ) nounwind readnone ; <<8 x i16>> [#uses=1] + %tmp10 = bitcast <8 x i16> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1] + ret <2 x i64> %tmp10 +} + +define <2 x i64> @t3(<2 x i64> %b1, i32 %c) nounwind { +entry: + %tmp2 = bitcast <2 x i64> %b1 to <8 x i16> ; <<8 x i16>> [#uses=1] + %tmp4 = insertelement <4 x i32> undef, i32 %c, i32 0 ; <<4 x i32>> [#uses=1] + %tmp8 = bitcast <4 x i32> %tmp4 to <8 x i16> ; <<8 x i16>> [#uses=1] + %tmp9 = tail call <8 x i16> @llvm.x86.sse2.psra.w( <8 x i16> %tmp2, <8 x i16> %tmp8 ) ; <<8 x i16>> [#uses=1] + %tmp11 = bitcast <8 x i16> %tmp9 to <2 x i64> ; <<2 x i64>> [#uses=1] + ret <2 x i64> %tmp11 +} + +declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone + +define <2 x i64> @t2(<2 x i64> %b1, <2 x i64> %c) nounwind { +entry: + %tmp9 = tail call <2 x i64> @llvm.x86.sse2.psrl.q( <2 x i64> %b1, <2 x i64> %c ) nounwind readnone ; <<2 x i64>> [#uses=1] + ret <2 x i64> %tmp9 +} + +declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone + +declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone |