diff options
| -rw-r--r-- | .gitignore | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 1 |
3 files changed, 8 insertions, 0 deletions
@@ -17,11 +17,13 @@ *.pyc # vim swap files .*.swp +*.patch #==============================================================================# # Explicit files to ignore (only matches one). #==============================================================================# .gitusers +.svn autom4te.cache cscope.files cscope.out diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 0c0b9ab..77650c7 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -95,6 +95,9 @@ MipsTargetLowering(MipsTargetMachine &TM) addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); + if (HasMips64) + addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); + // When dealing with single precision only, use libcalls if (!Subtarget->isSingleFloat()) { if (HasMips64) @@ -2260,6 +2263,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, if (RegVT == MVT::i32) RC = Mips::CPURegsRegisterClass; + else if (RegVT == MVT::i64) + RC = Mips::CPU64RegsRegisterClass; else if (RegVT == MVT::f32) RC = Mips::FGR32RegisterClass; else if (RegVT == MVT::f64) { diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 101a7ce..454b636 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -879,4 +879,5 @@ def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; //===----------------------------------------------------------------------===// include "MipsInstrFPU.td" +include "Mips64InstrInfo.td" |