diff options
| -rw-r--r-- | lib/CodeGen/MachineLICM.cpp | 8 | ||||
| -rw-r--r-- | test/CodeGen/SystemZ/asm-17.ll | 22 |
2 files changed, 26 insertions, 4 deletions
diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 6ad4e39..596b7a3 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -468,12 +468,12 @@ void MachineLICM::ProcessMI(MachineInstr *MI, for (MCRegAliasIterator AS(Reg, TRI, true); AS.isValid(); ++AS) { if (PhysRegDefs.test(*AS)) PhysRegClobbers.set(*AS); - if (PhysRegClobbers.test(*AS)) - // MI defined register is seen defined by another instruction in - // the loop, it cannot be a LICM candidate. - RuledOut = true; PhysRegDefs.set(*AS); } + if (PhysRegClobbers.test(Reg)) + // MI defined register is seen defined by another instruction in + // the loop, it cannot be a LICM candidate. + RuledOut = true; } // Only consider reloads for now and remats which do not have register diff --git a/test/CodeGen/SystemZ/asm-17.ll b/test/CodeGen/SystemZ/asm-17.ll index 33234fc..86b0bbf 100644 --- a/test/CodeGen/SystemZ/asm-17.ll +++ b/test/CodeGen/SystemZ/asm-17.ll @@ -80,3 +80,25 @@ define float @f7(float %in) { call void asm sideeffect "blah", "~{f0},~{cc}"() ret float %in } + +; Test that both registers in a GR128 pair get hoisted. +define void @f8(i32 %count) { +; CHECK-LABE: f8 +; CHECK-DAG: lhi %r0, 0 +; CHECK-DAG: lhi %r1, 1 +; CHECK: %loop +; CHECK-NOT: %r +; CHECK: blah %r0, %r1 +entry: + br label %loop + +loop: + %this = phi i32 [ %count, %entry ], [ %next, %loop ] + call void asm sideeffect "blah $0, $1", "{r0},{r1}" (i32 0, i32 1) + %next = sub i32 %this, 1 + %cmp = icmp ne i32 %next, 0 + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} |