diff options
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 4 | ||||
| -rw-r--r-- | test/CodeGen/XCore/2011-08-01-VarargsBug.ll | 17 |
2 files changed, 19 insertions, 2 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 21a119e..d23cfe0 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1148,10 +1148,10 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, int offset = 0; // Save remaining registers, storing higher register numbers at a higher // address - for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) { + for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { // Create a stack slot int FI = MFI->CreateFixedObject(4, offset, true); - if (i == FirstVAReg) { + if (i == (int)FirstVAReg) { XFI->setVarArgsFrameIndex(FI); } offset -= StackSlotSize; diff --git a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll new file mode 100644 index 0000000..2076057 --- /dev/null +++ b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +define void @_Z1fz(...) { +entry: +; CHECK: _Z1fz: +; CHECK: extsp 3 +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: stw r[[REG:[0-3]{1,1}]] +; CHECK: , sp{{\[}}[[REG]]{{\]}} +; CHECK: ldaw sp, sp[3] +; CHECK: retsp 0 + ret void +} |