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-rw-r--r--lib/Target/ARM/README.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index c155e20..8af07cc 100644
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -470,4 +470,9 @@ More register scavenging work:
//===---------------------------------------------------------------------===//
-Teach LSR about ARM addressing modes.
+More LSR enhancements possible:
+
+1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
+ in a load / store.
+2. Allow iv reuse even when a type conversion is required. For example, i8
+ and i32 load / store addressing modes are identical.