diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 8 |
3 files changed, 15 insertions, 7 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 5a6077a..0e719f8 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1102,14 +1102,8 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) { } // fold (sub x, x) -> 0 - if (N0 == N1) { - if (AfterLegalize && ISD::isBuildVectorAllZeros(N0.Val)) - // For example, zero vectors might be normalized to a particular vector - // type to ensure they are CSE'd. Avoid issuing zero vector nodes of - // *unexpected* type after legalization. - return N0; + if (N0 == N1) return DAG.getConstant(0, N->getValueType(0)); - } // fold (sub c1, c2) -> c1-c2 if (N0C && N1C) return DAG.getNode(ISD::SUB, VT, N0, N1); diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index 65013b3..0a18fa5 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -510,6 +510,12 @@ let isReMaterializable = 1 in { [(set VR64:$dst, (v2i32 immAllOnesV))]>; } +let Predicates = [HasMMX] in { + def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>; + def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>; + def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>; +} + //===----------------------------------------------------------------------===// // Non-Instruction Patterns //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 55d92bd..0ca9c69 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -969,6 +969,14 @@ def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "xorps\t$dst, $dst", [(set VR128:$dst, (v4i32 immAllZerosV))]>; +let Predicates = [HasSSE1] in { + def : Pat<(v2i64 immAllZerosV), (V_SET0)>; + def : Pat<(v8i16 immAllZerosV), (V_SET0)>; + def : Pat<(v16i8 immAllZerosV), (V_SET0)>; + def : Pat<(v2f64 immAllZerosV), (V_SET0)>; + def : Pat<(v4f32 immAllZerosV), (V_SET0)>; +} + // FR32 to 128-bit vector conversion. def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src), "movss\t{$src, $dst|$dst, $src}", |