diff options
| -rw-r--r-- | lib/CodeGen/MachOWriter.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 12 |
2 files changed, 10 insertions, 10 deletions
diff --git a/lib/CodeGen/MachOWriter.cpp b/lib/CodeGen/MachOWriter.cpp index a34204f..bb15a22 100644 --- a/lib/CodeGen/MachOWriter.cpp +++ b/lib/CodeGen/MachOWriter.cpp @@ -264,8 +264,8 @@ void MachOCodeEmitter::emitConstantPool(MachineConstantPool *MCP) { if (CP.empty()) return; // FIXME: handle PIC codegen - bool isPIC = TM.getRelocationModel() == Reloc::PIC_; - assert(!isPIC && "PIC codegen not yet handled for mach-o jump tables!"); + assert(TM.getRelocationModel() != Reloc::PIC_ && + "PIC codegen not yet handled for mach-o jump tables!"); // Although there is no strict necessity that I am aware of, we will do what // gcc for OS X does and put each constant pool entry in a section of constant @@ -305,8 +305,8 @@ void MachOCodeEmitter::emitJumpTables(MachineJumpTableInfo *MJTI) { if (JT.empty()) return; // FIXME: handle PIC codegen - bool isPIC = TM.getRelocationModel() == Reloc::PIC_; - assert(!isPIC && "PIC codegen not yet handled for mach-o jump tables!"); + assert(TM.getRelocationModel() != Reloc::PIC_ && + "PIC codegen not yet handled for mach-o jump tables!"); MachOWriter::MachOSection *Sec = MOW.getJumpTableSection(); unsigned TextSecIndex = MOW.getTextSection()->Index; diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 03fb8dc..c4b45bf 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -1219,14 +1219,14 @@ bool X86FastISel::X86SelectCall(Instruction *I) { case CCValAssign::SExt: { bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), Arg, ArgVT, Arg); - assert(Emitted && "Failed to emit a sext!"); + assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; ArgVT = VA.getLocVT(); break; } case CCValAssign::ZExt: { bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), Arg, ArgVT, Arg); - assert(Emitted && "Failed to emit a zext!"); + assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; ArgVT = VA.getLocVT(); break; } @@ -1240,7 +1240,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), Arg, ArgVT, Arg); - assert(Emitted && "Failed to emit a aext!"); + assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; ArgVT = VA.getLocVT(); break; } @@ -1250,7 +1250,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), Arg, RC, RC); - assert(Emitted && "Failed to emit a copy instruction!"); + assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; RegArgs.push_back(VA.getLocReg()); } else { unsigned LocMemOffset = VA.getLocMemOffset(); @@ -1277,7 +1277,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { TargetRegisterClass *RC = X86::GR32RegisterClass; unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); - assert(Emitted && "Failed to emit a copy instruction!"); + assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; } // Issue the call. @@ -1328,7 +1328,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { unsigned ResultReg = createResultReg(DstRC); bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, RVLocs[0].getLocReg(), DstRC, SrcRC); - assert(Emitted && "Failed to emit a copy instruction!"); + assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; if (CopyVT != RVLocs[0].getValVT()) { // Round the F80 the right size, which also moves to the appropriate xmm // register. This is accomplished by storing the F80 value in memory and |