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-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp17
-rw-r--r--test/CodeGen/X86/2012-12-1-merge-multiple.ll31
2 files changed, 46 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5659069..438e23d 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8157,8 +8157,21 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
// Only perform this optimization before the types are legal, because we
// don't want to perform this optimization on every DAGCombine invocation.
- if (!LegalTypes && MergeConsecutiveStores(ST))
- return SDValue(N, 0);
+ if (!LegalTypes) {
+ bool EverChanged = false;
+
+ do {
+ // There can be multiple store sequences on the same chain.
+ // Keep trying to merge store sequences until we are unable to do so
+ // or until we merge the last store on the chain.
+ bool Changed = MergeConsecutiveStores(ST);
+ EverChanged |= Changed;
+ if (!Changed) break;
+ } while (ST->getOpcode() != ISD::DELETED_NODE);
+
+ if (EverChanged)
+ return SDValue(N, 0);
+ }
return ReduceLoadOpStoreWidth(N);
}
diff --git a/test/CodeGen/X86/2012-12-1-merge-multiple.ll b/test/CodeGen/X86/2012-12-1-merge-multiple.ll
new file mode 100644
index 0000000..5931c3d
--- /dev/null
+++ b/test/CodeGen/X86/2012-12-1-merge-multiple.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win64 | FileCheck %s
+
+; CHECK: multiple_stores_on_chain
+; CHECK: movabsq
+; CHECK: movq
+; CHECK: movabsq
+; CHECK: movq
+; CHECK: ret
+define void @multiple_stores_on_chain(i16 * %A) {
+entry:
+ %a0 = getelementptr inbounds i16* %A, i64 0
+ %a1 = getelementptr inbounds i16* %A, i64 1
+ %a2 = getelementptr inbounds i16* %A, i64 2
+ %a3 = getelementptr inbounds i16* %A, i64 3
+ %a4 = getelementptr inbounds i16* %A, i64 4
+ %a5 = getelementptr inbounds i16* %A, i64 5
+ %a6 = getelementptr inbounds i16* %A, i64 6
+ %a7 = getelementptr inbounds i16* %A, i64 7
+
+ store i16 0, i16* %a0
+ store i16 1, i16* %a1
+ store i16 2, i16* %a2
+ store i16 3, i16* %a3
+ store i16 4, i16* %a4
+ store i16 5, i16* %a5
+ store i16 6, i16* %a6
+ store i16 7, i16* %a7
+
+ ret void
+}
+