diff options
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsCondMov.td | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 83322ea..4338279 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -66,7 +66,7 @@ multiclass AtomicCmpSwap64<PatFrag Op, string Width> { } } } -let usesCustomInserter = 1, Predicates = [HasMips64, HasStandardEncoding], +let usesCustomInserter = 1, Predicates = [HasStandardEncoding], DecoderNamespace = "Mips64" in { defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">; defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">; diff --git a/lib/Target/Mips/MipsCondMov.td b/lib/Target/Mips/MipsCondMov.td index b12b1f2..67be5d6 100644 --- a/lib/Target/Mips/MipsCondMov.td +++ b/lib/Target/Mips/MipsCondMov.td @@ -107,7 +107,7 @@ multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst, // Instantiation of instructions. def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">; -let Predicates = [HasMips64, HasStandardEncoding], +let Predicates = [HasStandardEncoding], DecoderNamespace = "Mips64" in { def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">; def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> { @@ -119,7 +119,7 @@ let Predicates = [HasMips64, HasStandardEncoding], } def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">; -let Predicates = [HasMips64, HasStandardEncoding], +let Predicates = [HasStandardEncoding], DecoderNamespace = "Mips64" in { def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">; def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> { diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 9bf5d6b..c47dbff 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1084,7 +1084,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>; // MUL is a assembly macro in the current used ISAs. In recent ISA's // it is a real instruction. def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, - Requires<[HasMips32, HasStandardEncoding]>; + Requires<[HasStandardEncoding]>; def RDHWR : ReadHardware<CPURegs, HWRegs>; |