diff options
| -rw-r--r-- | include/llvm/IR/IntrinsicsMips.td | 3 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsMSAInstrInfo.td | 12 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSEISelDAGToDAG.cpp | 16 | ||||
| -rw-r--r-- | test/CodeGen/Mips/msa/elm_move.ll | 24 |
4 files changed, 55 insertions, 0 deletions
diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td index 0bcbbd8..6e03a19 100644 --- a/include/llvm/IR/IntrinsicsMips.td +++ b/include/llvm/IR/IntrinsicsMips.td @@ -1344,6 +1344,9 @@ def int_mips_mod_u_w : GCCBuiltin<"__builtin_msa_mod_u_w">, def int_mips_mod_u_d : GCCBuiltin<"__builtin_msa_mod_u_d">, Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>; +def int_mips_move_v : GCCBuiltin<"__builtin_msa_move_v">, + Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; + def int_mips_msub_q_h : GCCBuiltin<"__builtin_msa_msub_q_h">, Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>; diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index e53b29e..eb95c78 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -542,6 +542,8 @@ class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; +class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; + class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; @@ -1852,6 +1854,14 @@ class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", int_mips_mod_u_w, NoItinerary, class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", int_mips_mod_u_d, NoItinerary, MSA128D, MSA128D>; +class MOVE_V_DESC { + dag OutOperandList = (outs MSA128B:$wd); + dag InOperandList = (ins MSA128B:$ws); + string AsmString = "move.v\t$wd, $ws"; + list<dag> Pattern = []; + InstrItinClass Itinerary = NoItinerary; +} + class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, NoItinerary, MSA128H, MSA128H>; class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, @@ -2689,6 +2699,8 @@ def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC, Requires<[HasMSA]>; def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC, Requires<[HasMSA]>; def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC, Requires<[HasMSA]>; +def MOVE_V : MOVE_V_ENC, MOVE_V_DESC, Requires<[HasMSA]>; + def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC, Requires<[HasMSA]>; def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC, Requires<[HasMSA]>; diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 221aeda..27fcaa3 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -463,6 +463,22 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) { break; } + case ISD::INTRINSIC_WO_CHAIN: { + switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) { + default: + break; + + case Intrinsic::mips_move_v: + // Like an assignment but will always produce a move.v even if + // unnecessary. + return std::make_pair(true, + CurDAG->getMachineNode(Mips::MOVE_V, DL, + Node->getValueType(0), + Node->getOperand(1))); + } + break; + } + case ISD::INTRINSIC_VOID: { switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { default: diff --git a/test/CodeGen/Mips/msa/elm_move.ll b/test/CodeGen/Mips/msa/elm_move.ll new file mode 100644 index 0000000..2f1763b --- /dev/null +++ b/test/CodeGen/Mips/msa/elm_move.ll @@ -0,0 +1,24 @@ +; Test the MSA move intrinsics (which are encoded with the ELM instruction +; format). + +; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s + +@llvm_mips_move_vb_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 +@llvm_mips_move_vb_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 + +define void @llvm_mips_move_vb_test() nounwind { +entry: + %0 = load <16 x i8>* @llvm_mips_move_vb_ARG1 + %1 = tail call <16 x i8> @llvm.mips.move.v(<16 x i8> %0) + store <16 x i8> %1, <16 x i8>* @llvm_mips_move_vb_RES + ret void +} + +declare <16 x i8> @llvm.mips.move.v(<16 x i8>) nounwind + +; CHECK: llvm_mips_move_vb_test: +; CHECK: ld.b +; CHECK: move.v +; CHECK: st.b +; CHECK: .size llvm_mips_move_vb_test +; |