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-rw-r--r--lib/Target/R600/AMDGPUIndirectAddressing.cpp4
-rw-r--r--lib/Target/R600/AMDGPUInstrInfo.cpp2
-rw-r--r--lib/Target/R600/AMDGPURegisterInfo.cpp6
-rw-r--r--lib/Target/R600/AMDGPURegisterInfo.h3
-rw-r--r--lib/Target/R600/AMDILCFGStructurizer.cpp19
-rw-r--r--lib/Target/R600/R600ControlFlowFinalizer.cpp16
-rw-r--r--lib/Target/R600/R600EmitClauseMarkers.cpp4
-rw-r--r--lib/Target/R600/R600ExpandSpecialInstrs.cpp3
-rw-r--r--lib/Target/R600/R600ISelLowering.cpp8
-rw-r--r--lib/Target/R600/R600ISelLowering.h2
-rw-r--r--lib/Target/R600/R600InstrInfo.cpp2
-rw-r--r--lib/Target/R600/R600OptimizeVectorRegisters.cpp3
-rw-r--r--lib/Target/R600/R600RegisterInfo.cpp11
-rw-r--r--lib/Target/R600/R600RegisterInfo.h4
-rw-r--r--lib/Target/R600/SIISelLowering.cpp13
-rw-r--r--lib/Target/R600/SIISelLowering.h3
-rw-r--r--lib/Target/R600/SIInsertWaits.cpp16
-rw-r--r--lib/Target/R600/SIInstrInfo.cpp2
-rw-r--r--lib/Target/R600/SILowerControlFlow.cpp5
-rw-r--r--lib/Target/R600/SIRegisterInfo.cpp8
-rw-r--r--lib/Target/R600/SIRegisterInfo.h4
21 files changed, 75 insertions, 63 deletions
diff --git a/lib/Target/R600/AMDGPUIndirectAddressing.cpp b/lib/Target/R600/AMDGPUIndirectAddressing.cpp
index 14b9e4f..3ce3ecf 100644
--- a/lib/Target/R600/AMDGPUIndirectAddressing.cpp
+++ b/lib/Target/R600/AMDGPUIndirectAddressing.cpp
@@ -39,7 +39,7 @@ private:
public:
AMDGPUIndirectAddressingPass(TargetMachine &tm) :
MachineFunctionPass(ID),
- TII(static_cast<const AMDGPUInstrInfo*>(tm.getInstrInfo()))
+ TII(0)
{ }
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -59,6 +59,8 @@ FunctionPass *llvm::createAMDGPUIndirectAddressingPass(TargetMachine &tm) {
bool AMDGPUIndirectAddressingPass::runOnMachineFunction(MachineFunction &MF) {
MachineRegisterInfo &MRI = MF.getRegInfo();
+ TII = static_cast<const AMDGPUInstrInfo*>(MF.getTarget().getInstrInfo());
+
int IndirectBegin = TII->getIndirectIndexBegin(MF);
int IndirectEnd = TII->getIndirectIndexEnd(MF);
diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp
index 45d886d..47e8c70 100644
--- a/lib/Target/R600/AMDGPUInstrInfo.cpp
+++ b/lib/Target/R600/AMDGPUInstrInfo.cpp
@@ -28,7 +28,7 @@
using namespace llvm;
AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm)
- : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { }
+ : AMDGPUGenInstrInfo(0,0), RI(tm), TM(tm) { }
const AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const {
return RI;
diff --git a/lib/Target/R600/AMDGPURegisterInfo.cpp b/lib/Target/R600/AMDGPURegisterInfo.cpp
index fe994d2..3402092 100644
--- a/lib/Target/R600/AMDGPURegisterInfo.cpp
+++ b/lib/Target/R600/AMDGPURegisterInfo.cpp
@@ -17,11 +17,9 @@
using namespace llvm;
-AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm,
- const TargetInstrInfo &tii)
+AMDGPURegisterInfo::AMDGPURegisterInfo(TargetMachine &tm)
: AMDGPUGenRegisterInfo(0),
- TM(tm),
- TII(tii)
+ TM(tm)
{ }
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/R600/AMDGPURegisterInfo.h b/lib/Target/R600/AMDGPURegisterInfo.h
index 1fc88e7..7cbd34b 100644
--- a/lib/Target/R600/AMDGPURegisterInfo.h
+++ b/lib/Target/R600/AMDGPURegisterInfo.h
@@ -30,10 +30,9 @@ class TargetInstrInfo;
struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
TargetMachine &TM;
- const TargetInstrInfo &TII;
static const uint16_t CalleeSavedReg;
- AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
+ AMDGPURegisterInfo(TargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const {
assert(!"Unimplemented"); return BitVector();
diff --git a/lib/Target/R600/AMDILCFGStructurizer.cpp b/lib/Target/R600/AMDILCFGStructurizer.cpp
index fcb5b7e..ea1a07e 100644
--- a/lib/Target/R600/AMDILCFGStructurizer.cpp
+++ b/lib/Target/R600/AMDILCFGStructurizer.cpp
@@ -2472,23 +2472,26 @@ public:
protected:
TargetMachine &TM;
- const TargetInstrInfo *TII;
- const AMDGPURegisterInfo *TRI;
public:
AMDGPUCFGStructurizer(char &pid, TargetMachine &tm);
const TargetInstrInfo *getTargetInstrInfo() const;
+ const AMDGPURegisterInfo *getTargetRegisterInfo() const;
};
} // end anonymous namespace
AMDGPUCFGStructurizer::AMDGPUCFGStructurizer(char &pid, TargetMachine &tm)
-: MachineFunctionPass(pid), TM(tm), TII(tm.getInstrInfo()),
- TRI(static_cast<const AMDGPURegisterInfo *>(tm.getRegisterInfo())) {
+ : MachineFunctionPass(pid), TM(tm) {
}
const TargetInstrInfo *AMDGPUCFGStructurizer::getTargetInstrInfo() const {
- return TII;
+ return TM.getInstrInfo();
+}
+
+const AMDGPURegisterInfo *AMDGPUCFGStructurizer::getTargetRegisterInfo() const {
+ return static_cast<const AMDGPURegisterInfo *>(TM.getRegisterInfo());
}
+
//===----------------------------------------------------------------------===//
//
// CFGPrepare
@@ -3017,7 +3020,8 @@ FunctionPass *llvm::createAMDGPUCFGPreparationPass(TargetMachine &tm) {
}
bool AMDGPUCFGPrepare::runOnMachineFunction(MachineFunction &func) {
- return CFGStructurizer<AMDGPUCFGStructurizer>().prepare(func, *this, TRI);
+ return CFGStructurizer<AMDGPUCFGStructurizer>().prepare(func, *this,
+ getTargetRegisterInfo());
}
// createAMDGPUCFGStructurizerPass- Returns a pass
@@ -3026,5 +3030,6 @@ FunctionPass *llvm::createAMDGPUCFGStructurizerPass(TargetMachine &tm) {
}
bool AMDGPUCFGPerform::runOnMachineFunction(MachineFunction &func) {
- return CFGStructurizer<AMDGPUCFGStructurizer>().run(func, *this, TRI);
+ return CFGStructurizer<AMDGPUCFGStructurizer>().run(func, *this,
+ getTargetRegisterInfo());
}
diff --git a/lib/Target/R600/R600ControlFlowFinalizer.cpp b/lib/Target/R600/R600ControlFlowFinalizer.cpp
index f229613..3d448bf 100644
--- a/lib/Target/R600/R600ControlFlowFinalizer.cpp
+++ b/lib/Target/R600/R600ControlFlowFinalizer.cpp
@@ -49,7 +49,7 @@ private:
static char ID;
const R600InstrInfo *TII;
- const R600RegisterInfo &TRI;
+ const R600RegisterInfo *TRI;
unsigned MaxFetchInst;
const AMDGPUSubtarget &ST;
@@ -122,8 +122,8 @@ private:
if (AMDGPU::R600_Reg128RegClass.contains(Reg))
DstMI = Reg;
else
- DstMI = TRI.getMatchingSuperReg(Reg,
- TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
+ DstMI = TRI->getMatchingSuperReg(Reg,
+ TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
&AMDGPU::R600_Reg128RegClass);
}
if (MO.isUse()) {
@@ -131,8 +131,8 @@ private:
if (AMDGPU::R600_Reg128RegClass.contains(Reg))
SrcMI = Reg;
else
- SrcMI = TRI.getMatchingSuperReg(Reg,
- TRI.getSubRegFromChannel(TRI.getHWRegChan(Reg)),
+ SrcMI = TRI->getMatchingSuperReg(Reg,
+ TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
&AMDGPU::R600_Reg128RegClass);
}
}
@@ -318,14 +318,16 @@ private:
public:
R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID),
- TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())),
- TRI(TII->getRegisterInfo()),
+ TII (0), TRI(0),
ST(tm.getSubtarget<AMDGPUSubtarget>()) {
const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
MaxFetchInst = ST.getTexVTXClauseSize();
}
virtual bool runOnMachineFunction(MachineFunction &MF) {
+ TII=static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
+ TRI=static_cast<const R600RegisterInfo *>(MF.getTarget().getRegisterInfo());
+
unsigned MaxStack = 0;
unsigned CurrentStack = 0;
bool HasPush = false;
diff --git a/lib/Target/R600/R600EmitClauseMarkers.cpp b/lib/Target/R600/R600EmitClauseMarkers.cpp
index c9d8ed1..ff5ce5a 100644
--- a/lib/Target/R600/R600EmitClauseMarkers.cpp
+++ b/lib/Target/R600/R600EmitClauseMarkers.cpp
@@ -205,9 +205,11 @@ private:
public:
R600EmitClauseMarkersPass(TargetMachine &tm) : MachineFunctionPass(ID),
- TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
+ TII(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF) {
+ TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
+
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
BB != BB_E; ++BB) {
MachineBasicBlock &MBB = *BB;
diff --git a/lib/Target/R600/R600ExpandSpecialInstrs.cpp b/lib/Target/R600/R600ExpandSpecialInstrs.cpp
index 072ae3a..40c058f 100644
--- a/lib/Target/R600/R600ExpandSpecialInstrs.cpp
+++ b/lib/Target/R600/R600ExpandSpecialInstrs.cpp
@@ -38,7 +38,7 @@ private:
public:
R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
- TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
+ TII(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -56,6 +56,7 @@ FunctionPass *llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
}
bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
+ TII = static_cast<const R600InstrInfo *>(MF.getTarget().getInstrInfo());
const R600RegisterInfo &TRI = TII->getRegisterInfo();
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index 267f367..06c2100 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -26,8 +26,7 @@
using namespace llvm;
R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
- AMDGPUTargetLowering(TM),
- TII(static_cast<const R600InstrInfo*>(TM.getInstrInfo())) {
+ AMDGPUTargetLowering(TM) {
addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
@@ -117,6 +116,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
MachineFunction * MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
MachineBasicBlock::iterator I = *MI;
+ const R600InstrInfo *TII =
+ static_cast<const R600InstrInfo*>(MF->getTarget().getInstrInfo());
switch (MI->getOpcode()) {
default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
@@ -536,6 +537,9 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
MachineSDNode *interp;
if (ijb < 0) {
+ const MachineFunction &MF = DAG.getMachineFunction();
+ const R600InstrInfo *TII =
+ static_cast<const R600InstrInfo*>(MF.getTarget().getInstrInfo());
interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
return DAG.getTargetExtractSubreg(
diff --git a/lib/Target/R600/R600ISelLowering.h b/lib/Target/R600/R600ISelLowering.h
index 2904396..d4ba4c8 100644
--- a/lib/Target/R600/R600ISelLowering.h
+++ b/lib/Target/R600/R600ISelLowering.h
@@ -40,8 +40,6 @@ public:
SmallVectorImpl<SDValue> &InVals) const;
virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const;
private:
- const R600InstrInfo * TII;
-
/// Each OpenCL kernel has nine implicit parameters that are stored in the
/// first nine dwords of a Vertex Buffer. These implicit parameters are
/// lowered to load instructions which retreive the values from the Vertex
diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp
index d915f40..421b75d 100644
--- a/lib/Target/R600/R600InstrInfo.cpp
+++ b/lib/Target/R600/R600InstrInfo.cpp
@@ -30,7 +30,7 @@ using namespace llvm;
R600InstrInfo::R600InstrInfo(AMDGPUTargetMachine &tm)
: AMDGPUInstrInfo(tm),
- RI(tm, *this),
+ RI(tm),
ST(tm.getSubtarget<AMDGPUSubtarget>())
{ }
diff --git a/lib/Target/R600/R600OptimizeVectorRegisters.cpp b/lib/Target/R600/R600OptimizeVectorRegisters.cpp
index 726cfbc..4636426 100644
--- a/lib/Target/R600/R600OptimizeVectorRegisters.cpp
+++ b/lib/Target/R600/R600OptimizeVectorRegisters.cpp
@@ -104,7 +104,7 @@ private:
public:
static char ID;
R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
- TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
+ TII(0) { }
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
@@ -314,6 +314,7 @@ void R600VectorRegMerger::trackRSI(const RegSeqInfo &RSI) {
}
bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
+ TII = static_cast<const R600InstrInfo *>(Fn.getTarget().getInstrInfo());
MRI = &(Fn.getRegInfo());
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
diff --git a/lib/Target/R600/R600RegisterInfo.cpp b/lib/Target/R600/R600RegisterInfo.cpp
index 7d13420..a42043b 100644
--- a/lib/Target/R600/R600RegisterInfo.cpp
+++ b/lib/Target/R600/R600RegisterInfo.cpp
@@ -20,11 +20,9 @@
using namespace llvm;
-R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
- const TargetInstrInfo &tii)
-: AMDGPURegisterInfo(tm, tii),
- TM(tm),
- TII(tii)
+R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm)
+: AMDGPURegisterInfo(tm),
+ TM(tm)
{ RCW.RegWeight = 0; RCW.WeightLimit = 0;}
BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
@@ -55,7 +53,8 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(*I);
}
- const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII);
+ const R600InstrInfo *RII =
+ static_cast<const R600InstrInfo*>(TM.getInstrInfo());
std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF);
for (std::vector<unsigned>::iterator I = IndirectRegs.begin(),
E = IndirectRegs.end();
diff --git a/lib/Target/R600/R600RegisterInfo.h b/lib/Target/R600/R600RegisterInfo.h
index 1270a1e..9b286ee 100644
--- a/lib/Target/R600/R600RegisterInfo.h
+++ b/lib/Target/R600/R600RegisterInfo.h
@@ -21,14 +21,12 @@
namespace llvm {
class R600TargetMachine;
-class TargetInstrInfo;
struct R600RegisterInfo : public AMDGPURegisterInfo {
AMDGPUTargetMachine &TM;
- const TargetInstrInfo &TII;
RegClassWeight RCW;
- R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+ R600RegisterInfo(AMDGPUTargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
index ac6a4c3..0530756 100644
--- a/lib/Target/R600/SIISelLowering.cpp
+++ b/lib/Target/R600/SIISelLowering.cpp
@@ -30,9 +30,7 @@ const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
using namespace llvm;
SITargetLowering::SITargetLowering(TargetMachine &TM) :
- AMDGPUTargetLowering(TM),
- TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
- TRI(TM.getRegisterInfo()) {
+ AMDGPUTargetLowering(TM) {
addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
@@ -257,6 +255,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
case AMDGPU::BRANCH: return BB;
case AMDGPU::SI_ADDR64_RSRC: {
+ const SIInstrInfo *TII =
+ static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
unsigned SuperReg = MI->getOperand(0).getReg();
unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
@@ -582,6 +582,8 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
bool &ScalarSlotUsed) const {
MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
+ const SIInstrInfo *TII =
+ static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
return false;
@@ -621,7 +623,10 @@ bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
SDNode *Node = Op.getNode();
const TargetRegisterClass *OpClass;
+ const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
+ const SIInstrInfo *TII =
+ static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
if (OpClassID == -1) {
@@ -697,6 +702,8 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
// Original encoding (either e32 or e64)
int Opcode = Node->getMachineOpcode();
+ const SIInstrInfo *TII =
+ static_cast<const SIInstrInfo*>(getTargetMachine().getInstrInfo());
const MCInstrDesc *Desc = &TII->get(Opcode);
unsigned NumDefs = Desc->getNumDefs();
diff --git a/lib/Target/R600/SIISelLowering.h b/lib/Target/R600/SIISelLowering.h
index 9b263b9..78ae6a1 100644
--- a/lib/Target/R600/SIISelLowering.h
+++ b/lib/Target/R600/SIISelLowering.h
@@ -21,9 +21,6 @@
namespace llvm {
class SITargetLowering : public AMDGPUTargetLowering {
- const SIInstrInfo * TII;
- const TargetRegisterInfo * TRI;
-
SDValue LowerParameter(SelectionDAG &DAG, EVT VT, SDLoc DL,
SDValue Chain, unsigned Offset) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
diff --git a/lib/Target/R600/SIInsertWaits.cpp b/lib/Target/R600/SIInsertWaits.cpp
index 98bd3db..c36e1dc 100644
--- a/lib/Target/R600/SIInsertWaits.cpp
+++ b/lib/Target/R600/SIInsertWaits.cpp
@@ -47,7 +47,7 @@ class SIInsertWaits : public MachineFunctionPass {
private:
static char ID;
const SIInstrInfo *TII;
- const SIRegisterInfo &TRI;
+ const SIRegisterInfo *TRI;
const MachineRegisterInfo *MRI;
/// \brief Constant hardware limits
@@ -97,8 +97,8 @@ private:
public:
SIInsertWaits(TargetMachine &tm) :
MachineFunctionPass(ID),
- TII(static_cast<const SIInstrInfo*>(tm.getInstrInfo())),
- TRI(TII->getRegisterInfo()) { }
+ TII(0),
+ TRI(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -137,7 +137,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) {
assert(Op.isReg() && "First LGKM operand must be a register!");
unsigned Reg = Op.getReg();
- unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
+ unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
Result.Named.LGKM = Size > 4 ? 2 : 1;
} else {
@@ -182,12 +182,12 @@ RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) {
return std::make_pair(0, 0);
unsigned Reg = Op.getReg();
- unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize();
+ unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
assert(Size >= 4);
RegInterval Result;
- Result.first = TRI.getEncodingValue(Reg);
+ Result.first = TRI->getEncodingValue(Reg);
Result.second = Result.first + Size / 4;
return Result;
@@ -328,9 +328,11 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) {
}
bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) {
-
bool Changes = false;
+ TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo());
+ TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
MRI = &MF.getRegInfo();
WaitedOn = ZeroCounts;
diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
index 9a04c60..cb582a6 100644
--- a/lib/Target/R600/SIInstrInfo.cpp
+++ b/lib/Target/R600/SIInstrInfo.cpp
@@ -24,7 +24,7 @@ using namespace llvm;
SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
: AMDGPUInstrInfo(tm),
- RI(tm, *this)
+ RI(tm)
{ }
const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp
index 2b60eb9..5b434fb 100644
--- a/lib/Target/R600/SILowerControlFlow.cpp
+++ b/lib/Target/R600/SILowerControlFlow.cpp
@@ -91,8 +91,7 @@ private:
public:
SILowerControlFlowPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TRI(tm.getRegisterInfo()),
- TII(tm.getInstrInfo()) { }
+ MachineFunctionPass(ID), TRI(0), TII(0) { }
virtual bool runOnMachineFunction(MachineFunction &MF);
@@ -408,6 +407,8 @@ void SILowerControlFlowPass::IndirectDst(MachineInstr &MI) {
}
bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
+ TII = MF.getTarget().getInstrInfo();
+ TRI = MF.getTarget().getRegisterInfo();
bool HaveKill = false;
bool NeedWQM = false;
diff --git a/lib/Target/R600/SIRegisterInfo.cpp b/lib/Target/R600/SIRegisterInfo.cpp
index 99278ae..ddfc54e 100644
--- a/lib/Target/R600/SIRegisterInfo.cpp
+++ b/lib/Target/R600/SIRegisterInfo.cpp
@@ -18,11 +18,9 @@
using namespace llvm;
-SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm,
- const TargetInstrInfo &tii)
-: AMDGPURegisterInfo(tm, tii),
- TM(tm),
- TII(tii)
+SIRegisterInfo::SIRegisterInfo(AMDGPUTargetMachine &tm)
+: AMDGPURegisterInfo(tm),
+ TM(tm)
{ }
BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
diff --git a/lib/Target/R600/SIRegisterInfo.h b/lib/Target/R600/SIRegisterInfo.h
index caec228..c322f94 100644
--- a/lib/Target/R600/SIRegisterInfo.h
+++ b/lib/Target/R600/SIRegisterInfo.h
@@ -21,13 +21,11 @@
namespace llvm {
class AMDGPUTargetMachine;
-class TargetInstrInfo;
struct SIRegisterInfo : public AMDGPURegisterInfo {
AMDGPUTargetMachine &TM;
- const TargetInstrInfo &TII;
- SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+ SIRegisterInfo(AMDGPUTargetMachine &tm);
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
generated by cgit v1.1 at 2025-01-09 07:18:38 +0000