diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/machine-cse.ll | 4 |
2 files changed, 7 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index bcb0ffe..c2711c8 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2483,7 +2483,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) return getNode(OpOpcode, DL, VT, Operand.getNode()->getOperand(0)); else if (OpOpcode == ISD::UNDEF) - return getUNDEF(VT); + // sext(undef) = 0, because the top bits will all be the same. + return getConstant(0, VT); break; case ISD::ZERO_EXTEND: assert(VT.isInteger() && Operand.getValueType().isInteger() && @@ -2498,6 +2499,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) return getNode(ISD::ZERO_EXTEND, DL, VT, Operand.getNode()->getOperand(0)); + else if (OpOpcode == ISD::UNDEF) + // zext(undef) = 0, because the top bits will be zero. + return getConstant(0, VT); break; case ISD::ANY_EXTEND: assert(VT.isInteger() && Operand.getValueType().isInteger() && diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll index e284776..d819fc8 100644 --- a/test/CodeGen/X86/machine-cse.ll +++ b/test/CodeGen/X86/machine-cse.ll @@ -6,11 +6,11 @@ %struct.s2 = type { i32, i8*, i8*, [256 x %struct.s1*], [8 x i32], i64, i8*, i32, i64, i64, i32, %struct.s3*, %struct.s3*, [49 x i64] } %struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 } -define fastcc i8* @t(i64 %size) nounwind { +define fastcc i8* @t(i32 %base) nounwind { entry: ; CHECK: t: ; CHECK: leaq (%rax,%rax,4) - %0 = zext i32 undef to i64 + %0 = zext i32 %base to i64 %1 = getelementptr inbounds %struct.s2* null, i64 %0 br i1 undef, label %bb1, label %bb2 |