diff options
| -rw-r--r-- | lib/Target/Sparc/SparcAsmPrinter.cpp | 26 | ||||
| -rw-r--r-- | test/CodeGen/SPARC/64abi.ll | 16 |
2 files changed, 42 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index 3fe2b44..b695dd8 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -20,6 +20,7 @@ #include "llvm/ADT/SmallString.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" @@ -43,6 +44,7 @@ namespace { const char *Modifier = 0); void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); + virtual void EmitFunctionBodyStart(); virtual void EmitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream OS(Str); @@ -63,11 +65,35 @@ namespace { virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; + void EmitGlobalRegisterDecl(unsigned reg) { + SmallString<128> Str; + raw_svector_ostream OS(Str); + OS << "\t.register " + << "%" << StringRef(getRegisterName(reg)).lower() + << ", " + << ((reg == SP::G6 || reg == SP::G7)? "#ignore" : "#scratch"); + OutStreamer.EmitRawText(OS.str()); + } + }; } // end of anonymous namespace #include "SparcGenAsmWriter.inc" +void SparcAsmPrinter::EmitFunctionBodyStart() { + if (!TM.getSubtarget<SparcSubtarget>().is64Bit()) + return; + + const MachineRegisterInfo &MRI = MF->getRegInfo(); + const unsigned globalRegs[] = { SP::G2, SP::G3, SP::G6, SP::G7, 0 }; + for (unsigned i = 0; globalRegs[i] != 0; ++i) { + unsigned reg = globalRegs[i]; + if (!MRI.isPhysRegUsed(reg)) + continue; + EmitGlobalRegisterDecl(reg); + } +} + void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { const MachineOperand &MO = MI->getOperand (opNum); diff --git a/test/CodeGen/SPARC/64abi.ll b/test/CodeGen/SPARC/64abi.ll index 5a7eb40..00fb99a 100644 --- a/test/CodeGen/SPARC/64abi.ll +++ b/test/CodeGen/SPARC/64abi.ll @@ -376,3 +376,19 @@ define signext i32 @ret_nosext(i32 signext %a0) { define signext i32 @ret_nozext(i32 signext %a0) { ret i32 %a0 } + +; CHECK-LABEL: test_register_directive +; CHECK: .register %g2, #scratch +; CHECK: .register %g3, #scratch +; CHECK: .register %g6, #ignore +; CHECK: .register %g7, #ignore +; CHECK: add %i0, 2, %g2 +; CHECK: add %i0, 3, %g3 +define i32 @test_register_directive(i32 %i0) { +entry: + %0 = add nsw i32 %i0, 2 + %1 = add nsw i32 %i0, 3 + tail call void asm sideeffect "", "r,r,~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o6},~{o7},~{g1},~{g4},~{g5},~{g6},~{g7}"(i32 %0, i32 %1) + %2 = add nsw i32 %0, %1 + ret i32 %2 +} |