diff options
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 20 | ||||
| -rw-r--r-- | test/CodeGen/X86/split-select.ll | 7 |
2 files changed, 27 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index dfb7f30..da2c1dc 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -6225,6 +6225,26 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, } break; } + case ISD::SELECT: { + SDOperand Cond = Node->getOperand(0); + + SDOperand LL, LH, RL, RH; + SplitVectorOp(Node->getOperand(1), LL, LH); + SplitVectorOp(Node->getOperand(2), RL, RH); + + if (MVT::isVector(Cond.getValueType())) { + // Handle a vector merge. + SDOperand CL, CH; + SplitVectorOp(Cond, CL, CH); + Lo = DAG.getNode(Node->getOpcode(), NewVT, CL, LL, RL); + Hi = DAG.getNode(Node->getOpcode(), NewVT, CH, LH, RH); + } else { + // Handle a simple select with vector operands. + Lo = DAG.getNode(Node->getOpcode(), NewVT, Cond, LL, RL); + Hi = DAG.getNode(Node->getOpcode(), NewVT, Cond, LH, RH); + } + break; + } case ISD::ADD: case ISD::SUB: case ISD::MUL: diff --git a/test/CodeGen/X86/split-select.ll b/test/CodeGen/X86/split-select.ll new file mode 100644 index 0000000..6e2f6e6 --- /dev/null +++ b/test/CodeGen/X86/split-select.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=x86-64 | grep test | count 1 + +define void @foo(i1 %c, <2 x float> %a, <2 x float> %b, <2 x float>* %p) { + %x = select i1 %c, <2 x float> %a, <2 x float> %b + store <2 x float> %x, <2 x float>* %p + ret void +} |