diff options
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 16 | ||||
| -rw-r--r-- | test/CodeGen/XCore/ashr.ll | 76 |
2 files changed, 92 insertions, 0 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index d75cf9b..4b9ea7a 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -975,5 +975,21 @@ def : Pat<(mul GRRegs:$src, -3), def : Pat<(sra GRRegs:$src, 31), (ASHR_l2rus GRRegs:$src, 32)>; +def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), + (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; + +// setge X, 0 is canonicalized to setgt X, -1 +def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), + (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; + +def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), + (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; + +def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), + (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; + +def : Pat<(setgt GRRegs:$lhs, -1), + (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; + def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll new file mode 100644 index 0000000..d585e8b --- /dev/null +++ b/test/CodeGen/XCore/ashr.ll @@ -0,0 +1,76 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +define i32 @ashr(i32 %a, i32 %b) { + %1 = ashr i32 %a, %b + ret i32 %1 +} +; CHECK: ashr: +; CHECK-NEXT: ashr r0, r0, r1 + +define i32 @ashri1(i32 %a) { + %1 = ashr i32 %a, 24 + ret i32 %1 +} +; CHECK: ashri1: +; CHECK-NEXT: ashr r0, r0, 24 + +define i32 @ashri2(i32 %a) { + %1 = ashr i32 %a, 31 + ret i32 %1 +} +; CHECK: ashri2: +; CHECK-NEXT: ashr r0, r0, 32 + +define i32 @f1(i32 %a) { + %1 = icmp slt i32 %a, 0 + br i1 %1, label %less, label %not_less +less: + ret i32 10 +not_less: + ret i32 17 +} +; CHECK: f1: +; CHECK-NEXT: ashr r0, r0, 32 +; CHECK-NEXT: bf r0 + +define i32 @f2(i32 %a) { + %1 = icmp sge i32 %a, 0 + br i1 %1, label %greater, label %not_greater +greater: + ret i32 10 +not_greater: + ret i32 17 +} +; CHECK: f2: +; CHECK-NEXT: ashr r0, r0, 32 +; CHECK-NEXT: bt r0 + +define i32 @f3(i32 %a) { + %1 = icmp slt i32 %a, 0 + %2 = select i1 %1, i32 10, i32 17 + ret i32 %2 +} +; CHECK: f3: +; CHECK-NEXT: ashr r1, r0, 32 +; CHECK-NEXT: ldc r0, 10 +; CHECK-NEXT: bt r1 +; CHECK: ldc r0, 17 + +define i32 @f4(i32 %a) { + %1 = icmp sge i32 %a, 0 + %2 = select i1 %1, i32 10, i32 17 + ret i32 %2 +} +; CHECK: f4: +; CHECK-NEXT: ashr r1, r0, 32 +; CHECK-NEXT: ldc r0, 17 +; CHECK-NEXT: bt r1 +; CHECK: ldc r0, 10 + +define i32 @f5(i32 %a) { + %1 = icmp sge i32 %a, 0 + %2 = zext i1 %1 to i32 + ret i32 %2 +} +; CHECK: f5: +; CHECK-NEXT: ashr r0, r0, 32 +; CHECK-NEXT: eq r0, r0, 0 |