diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 23 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 38 |
2 files changed, 41 insertions, 20 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index d446109..b0fe8da 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -339,8 +339,8 @@ class XForm_16_ext<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx> let L = ppc64; } -class XForm_17<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx> - : I<name, opcode, ppc64, vmx> { +class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx, + dag OL, string asmstr> : I<"", opcode, ppc64, vmx> { field bits<3> BF; field bits<5> FRA; field bits<5> FRB; @@ -358,6 +358,8 @@ class XForm_17<string name, bits<6> opcode, bits<10> xo, bit ppc64, bit vmx> let Inst{16-20} = FRB; let Inst{21-30} = xo; let Inst{31} = 0; + let OperandList = OL; + let AsmString = asmstr; } class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx, @@ -573,8 +575,8 @@ class AForm_3<bits<6> opcode, bits<5> xo, bit rc, bit ppc64, bit vmx, dag OL, } // 1.7.13 M-Form -class MForm_1<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx> - : I<name, opcode, ppc64, vmx> { +class MForm_1<bits<6> opcode, bit rc, bit ppc64, bit vmx, + dag OL, string asmstr> : I<"", opcode, ppc64, vmx> { let ArgCount = 5; field bits<5> RS; field bits<5> RA; @@ -594,16 +596,19 @@ class MForm_1<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx> let Inst{21-25} = MB; let Inst{26-30} = ME; let Inst{31} = rc; + let OperandList = OL; + let AsmString = asmstr; } -class MForm_2<string name, bits<6> opcode, bit rc, bit ppc64, bit vmx> - : MForm_1<name, opcode, rc, ppc64, vmx> { +class MForm_2<bits<6> opcode, bit rc, bit ppc64, bit vmx, + dag OL, string asmstr> + : MForm_1<opcode, rc, ppc64, vmx, OL, asmstr> { let Arg2Type = Imm5.Value; } // 1.7.14 MD-Form -class MDForm_1<string name, bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx> - : I<name, opcode, ppc64, vmx> { +class MDForm_1<bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit vmx, + dag OL, string asmstr> : I<"", opcode, ppc64, vmx> { let ArgCount = 4; field bits<5> RS; field bits<5> RA; @@ -623,6 +628,8 @@ class MDForm_1<string name, bits<6> opcode, bits<3> xo, bit rc, bit ppc64, bit v let Inst{27-29} = xo; let Inst{30} = SH{0}; let Inst{31} = rc; + let OperandList = OL; + let AsmString = asmstr; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 41ef35b..d692745 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -96,20 +96,12 @@ def LD : DSForm_2<"ld", 58, 0, 1, 0>; def STD : DSForm_2<"std", 62, 0, 1, 0>; def STDU : DSForm_2<"stdu", 62, 1, 1, 0>; -def RLWNM : MForm_1<"rlwnm", 23, 0, 0, 0>; -def RLWIMI : MForm_2<"rlwimi", 20, 0, 0, 0>; -def RLWINM : MForm_2<"rlwinm", 21, 0, 0, 0>; -def SRWI : MForm_2<"srwi", 21, 0, 0, 0>; -def RLDICL : MDForm_1<"rldicl", 30, 0, 0, 1, 0>; -def RLDICR : MDForm_1<"rldicr", 30, 1, 0, 1, 0>; - def CMP : XForm_16<"cmp", 31, 0, 0, 0>; def CMPL : XForm_16<"cmpl", 31, 32, 0, 0>; def CMPW : XForm_16_ext<"cmpw", 31, 0, 0, 0>; def CMPD : XForm_16_ext<"cmpd", 31, 0, 1, 0>; def CMPLW : XForm_16_ext<"cmplw", 31, 32, 0, 0>; def CMPLD : XForm_16_ext<"cmpld", 31, 32, 1, 0>; -def FCMPU : XForm_17<"fcmpu", 63, 0, 0, 0>; // D-Form instructions. Most instructions that perform an operation on a // register and an immediate are of this type. @@ -208,10 +200,12 @@ def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS), "extsh $rA, $rS">; def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS), "extsw $rA, $rS">; -def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index), - "lfsx $dst, $base, $index">; -def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index), - "lfdx $dst, $base, $index">; +def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB), + "fcmpu $crD, $fA, $fB">; +def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index), + "lfsx $dst, $base, $index">; +def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index), + "lfdx $dst, $base, $index">; def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB), "fcfid $frD, $frB">; def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB), @@ -322,3 +316,23 @@ def FSUBS : AForm_2<59, 20, 0, 0, 0, (ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB), "fsubs $FRT, $FRA, $FRB">; +// M-Form instructions. rotate and mask instructions. +// +def RLWIMI : MForm_2<20, 0, 0, 0, + (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + "rlwimi $rA, $rS, $SH, $MB, $ME">; +def RLWINM : MForm_2<21, 0, 0, 0, + (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + "rlwinm $rA, $rS, $SH, $MB, $ME">; + + +// MD-Form instructions. 64 bit rotate instructions. +// +def RLDICL : MDForm_1<30, 0, 0, 1, 0, + (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$MB), + "rldicl $rA, $rS, $SH, $MB">; +def RLDICR : MDForm_1<30, 1, 0, 1, 0, + (ops GPRC:$rA, GPRC:$rS, u6imm:$SH, u6imm:$ME), + "rldicr $rA, $rS, $SH, $ME">; + + |