diff options
| -rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 16 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp | 8 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 8 |
3 files changed, 18 insertions, 14 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 446e74c..4b65bd2 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -48,8 +48,10 @@ namespace llvm { bool isArtificial : 1; // True iff it's an artificial ctrl dep added // during sched that may be safely deleted if // necessary. - SDep(SUnit *d, unsigned r, int t, bool c, bool a) - : Dep(d), Reg(r), Cost(t), isCtrl(c), isArtificial(a) {} + bool isAntiDep : 1; // True iff it's an anti-dependency (on a physical + // register. + SDep(SUnit *d, unsigned r, int t, bool c, bool a, bool anti) + : Dep(d), Reg(r), Cost(t), isCtrl(c), isArtificial(a), isAntiDep(anti) {} }; /// SUnit - Scheduling unit. This is a node in the scheduling DAG. @@ -140,15 +142,17 @@ namespace llvm { } /// addPred - This adds the specified node as a pred of the current node if - /// not already. This returns true if this is a new pred. + /// not already. It also adds the current node as a successor of the + /// specified node. This returns true if this is a new pred. bool addPred(SUnit *N, bool isCtrl, bool isArtificial, - unsigned PhyReg = 0, int Cost = 1) { + unsigned PhyReg = 0, int Cost = 1, bool isAntiDep = false) { for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i) if (Preds[i].Dep == N && Preds[i].isCtrl == isCtrl && Preds[i].isArtificial == isArtificial) return false; - Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isArtificial)); - N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, isArtificial)); + Preds.push_back(SDep(N, PhyReg, Cost, isCtrl, isArtificial, isAntiDep)); + N->Succs.push_back(SDep(this, PhyReg, Cost, isCtrl, + isArtificial, isAntiDep)); if (!isCtrl) { ++NumPreds; ++N->NumSuccs; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index f684c3e..55fd7e4 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -287,18 +287,18 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) { if (I->isCtrl) ChainPred = I->Dep; else if (I->Dep->getNode() && I->Dep->getNode()->isOperandOf(LoadNode)) - LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); + LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false)); else - NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); + NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false)); } for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { if (I->isCtrl) ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, - I->isCtrl, I->isArtificial)); + I->isCtrl, I->isArtificial, I->isAntiDep)); else NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, - I->isCtrl, I->isArtificial)); + I->isCtrl, I->isArtificial, I->isAntiDep)); } if (ChainPred) { diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index bdca21e..03a91cf 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -688,18 +688,18 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { if (I->isCtrl) ChainPred = I->Dep; else if (I->Dep->getNode() && I->Dep->getNode()->isOperandOf(LoadNode)) - LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); + LoadPreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false)); else - NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false)); + NodePreds.push_back(SDep(I->Dep, I->Reg, I->Cost, false, false, false)); } for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); I != E; ++I) { if (I->isCtrl) ChainSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, - I->isCtrl, I->isArtificial)); + I->isCtrl, I->isArtificial, I->isAntiDep)); else NodeSuccs.push_back(SDep(I->Dep, I->Reg, I->Cost, - I->isCtrl, I->isArtificial)); + I->isCtrl, I->isArtificial, I->isAntiDep)); } if (ChainPred) { |