diff options
| -rw-r--r-- | include/llvm/CodeGen/FastISel.h | 2 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/FastISel.cpp | 23 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 12 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 21 |
5 files changed, 26 insertions, 34 deletions
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index 4355113..3939594 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -17,7 +17,6 @@ #include "llvm/BasicBlock.h" #include "llvm/ADT/DenseMap.h" #include "llvm/CodeGen/SelectionDAGNodes.h" -#include <map> namespace llvm { @@ -53,7 +52,6 @@ public: BasicBlock::iterator SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End, DenseMap<const Value*, unsigned> &ValueMap, - std::map<const BasicBlock*, MachineBasicBlock *> &MBBMap, MachineBasicBlock *MBB); virtual ~FastISel(); diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index fb4de57..1462472 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -145,8 +145,6 @@ BasicBlock::iterator FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End, DenseMap<const Value*, unsigned> &ValueMap, - std::map<const BasicBlock*, - MachineBasicBlock *> &MBBMap, MachineBasicBlock *mbb) { MBB = mbb; BasicBlock::iterator I = Begin; @@ -197,24 +195,19 @@ FastISel::SelectInstructions(BasicBlock::iterator Begin, case Instruction::Br: { BranchInst *BI = cast<BranchInst>(I); + // For now, check for and handle just the most trivial case: an + // unconditional fall-through branch. if (BI->isUnconditional()) { - MachineFunction::iterator NextMBB = + MachineFunction::iterator NextMBB = next(MachineFunction::iterator(MBB)); - BasicBlock *LLVMSucc = BI->getSuccessor(0); - MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; - - if (NextMBB != MF.end() && MSucc == NextMBB) { - // The unconditional fall-through case, which needs no instructions. - } else { - // The unconditional branch case. - TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); + if (NextMBB != MF.end() && + NextMBB->getBasicBlock() == BI->getSuccessor(0)) { + MBB->addSuccessor(NextMBB); + break; } - MBB->addSuccessor(MSucc); - break; } - // Conditional branches are not handed yet. - // Halt "fast" selection and bail. + // Something more complicated. Halt "fast" selection and bail. return I; } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index e13cfc0..9304c0e 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -5113,7 +5113,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB, cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) { if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) { Begin = F->SelectInstructions(Begin, LLVMBB->end(), - FuncInfo.ValueMap, FuncInfo.MBBMap, BB); + FuncInfo.ValueMap, BB); // Clean up the FastISel object. TODO: Reorganize what data is // stored in the FastISel class itself and what is merely passed diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 446cfda..5e7c73c 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -1254,9 +1254,15 @@ def : Pat<(i64 (zext GR32:$src)), def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; // extload -def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; -def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>; -def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>; +def : Pat<(extloadi64i1 addr:$src), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src), + x86_subreg_8bit)>; +def : Pat<(extloadi64i8 addr:$src), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV8rm addr:$src), + x86_subreg_8bit)>; +def : Pat<(extloadi64i16 addr:$src), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV16rm addr:$src), + x86_subreg_16bit)>; def : Pat<(extloadi64i32 addr:$src), (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (MOV32rm addr:$src), x86_subreg_32bit)>; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index aa2fe09..e55edce 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2784,24 +2784,19 @@ def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; // extload bool -> extload byte def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>; -def : Pat<(extloadi16i1 addr:$src), - (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src), - x86_subreg_8bit)>; -def : Pat<(extloadi16i8 addr:$src), - (INSERT_SUBREG (i16 (IMPLICIT_DEF)), (MOV8rm addr:$src), - x86_subreg_8bit)>; -// For extloads with 32-bit results, chose instructions that -// define the whole 32 bits of the result, to avoid partial-register -// updates. +def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>, + Requires<[In32BitMode]>; def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; +def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>, + Requires<[In32BitMode]>; def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>; def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>; // anyext -def : Pat<(i16 (anyext GR8:$src)), - (INSERT_SUBREG (i16 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>; -def : Pat<(i32 (anyext GR8:$src)), - (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src, x86_subreg_8bit)>; +def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>, + Requires<[In32BitMode]>; +def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>, + Requires<[In32BitMode]>; def : Pat<(i32 (anyext GR16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>; |