diff options
| -rw-r--r-- | lib/Target/Mips/MipsSEISelLowering.cpp | 30 | ||||
| -rw-r--r-- | test/CodeGen/Mips/msa/basic_operations.ll | 11 | ||||
| -rw-r--r-- | test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll | 21 |
3 files changed, 48 insertions, 14 deletions
diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index 721b58a9..2c316e3 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -41,6 +41,22 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) if (HasMips64) addRegisterClass(MVT::i64, &Mips::GPR64RegClass); + if (Subtarget->hasDSP() || Subtarget->hasMSA()) { + // Expand all truncating stores and extending loads. + unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; + + for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { + for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) + setTruncStoreAction((MVT::SimpleValueType)VT0, + (MVT::SimpleValueType)VT1, Expand); + + setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); + setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); + setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); + } + } + if (Subtarget->hasDSP()) { MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; @@ -58,20 +74,6 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::BITCAST, VecTys[i], Legal); } - // Expand all truncating stores and extending loads. - unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; - unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; - - for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { - for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) - setTruncStoreAction((MVT::SimpleValueType)VT0, - (MVT::SimpleValueType)VT1, Expand); - - setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); - setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); - setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); - } - setTargetDAGCombine(ISD::SHL); setTargetDAGCombine(ISD::SRA); setTargetDAGCombine(ISD::SRL); diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll index c626b28..b0de05d 100644 --- a/test/CodeGen/Mips/msa/basic_operations.ll +++ b/test/CodeGen/Mips/msa/basic_operations.ll @@ -1,5 +1,6 @@ ; RUN: llc -march=mips -mattr=+msa < %s | FileCheck -check-prefix=MIPS32 %s +@v4i8 = global <4 x i8> <i8 0, i8 0, i8 0, i8 0> @v16i8 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> @v8i16 = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> @v4i32 = global <4 x i32> <i32 0, i32 0, i32 0, i32 0> @@ -454,3 +455,13 @@ define void @insert_v2i64(i64 %a) nounwind { ret void ; MIPS32: .size insert_v2i64 } + +define void @truncstore() nounwind { + ; MIPS32: truncstore: + + store volatile <4 x i8> <i8 -1, i8 -1, i8 -1, i8 -1>, <4 x i8>*@v4i8 + ; TODO: What code should be emitted? + + ret void + ; MIPS32: .size truncstore +} diff --git a/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll b/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll new file mode 100644 index 0000000..9eb4ff4 --- /dev/null +++ b/test/CodeGen/Mips/msa/llvm-stress-sz1-s742806235.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mips < %s +; RUN: llc -march=mips -mattr=+MSA < %s + +; This test originally failed to select code for a truncstore of a +; build_vector. +; It should at least successfully build. + +define void @autogen_SD742806235(i8*, i32*, i64*, i32, i64, i8) { +BB: + %A4 = alloca double + %A3 = alloca double + %A2 = alloca <8 x i8> + %A1 = alloca <4 x float> + %A = alloca i1 + store i8 %5, i8* %0 + store i8 %5, i8* %0 + store i8 %5, i8* %0 + store <8 x i8> <i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 -1>, <8 x i8>* %A2 + store i8 %5, i8* %0 + ret void +} |