diff options
| -rw-r--r-- | lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 22 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 18 | ||||
| -rw-r--r-- | test/MC/Mips/mips-alu-instructions.s | 4 |
3 files changed, 42 insertions, 2 deletions
diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 5b77d87..447e7dc 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -144,6 +144,9 @@ class MipsAsmParser : public MCTargetAsmParser { MipsAsmParser::OperandMatchResultTy parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands); + MipsAsmParser::OperandMatchResultTy + parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands); + bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand*> &Operands, unsigned RegKind); @@ -351,6 +354,7 @@ public: bool isToken() const { return Kind == k_Token; } bool isMem() const { return Kind == k_Memory; } bool isPtrReg() const { return Kind == k_PtrReg; } + bool isInvNum() const { return Kind == k_Immediate; } StringRef getToken() const { assert(Kind == k_Token && "Invalid access!"); @@ -1817,6 +1821,24 @@ MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { return parseRegs(Operands, (int) MipsOperand::Kind_CCRRegs); } +MipsAsmParser::OperandMatchResultTy +MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { + const MCExpr *IdVal; + // If the first token is '$' we may have register operand. + if (Parser.getTok().is(AsmToken::Dollar)) + return MatchOperand_NoMatch; + SMLoc S = Parser.getTok().getLoc(); + if (getParser().parseExpression(IdVal)) + return MatchOperand_ParseFail; + const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal); + assert( MCE && "Unexpected MCExpr type."); + int64_t Val = MCE->getValue(); + SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Operands.push_back(MipsOperand::CreateImm( + MCConstantExpr::Create(0 - Val, getContext()), S, E)); + return MatchOperand_Success; +} + MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) { MCSymbolRefExpr::VariantKind VK diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 1f80289..f92f333 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -282,11 +282,22 @@ def MipsMemAsmOperand : AsmOperandClass { let ParserMethod = "parseMemOperand"; } +def MipsInvertedImmoperand : AsmOperandClass { + let Name = "InvNum"; + let RenderMethod = "addImmOperands"; + let ParserMethod = "parseInvNum"; +} + def PtrRegAsmOperand : AsmOperandClass { let Name = "PtrReg"; let ParserMethod = "parsePtrReg"; } + +def InvertedImOperand : Operand<i32> { + let ParserMatchClass = MipsInvertedImmoperand; +} + // Address operand def mem : Operand<iPTR> { let PrintMethod = "printMemOperand"; @@ -1120,6 +1131,11 @@ def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : InstAlias<"sub, $rd, $rs, $imm", + (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; +def : InstAlias<"subu, $rd, $rs, $imm", + (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>; + //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// @@ -1139,8 +1155,6 @@ class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : !strconcat(instr_asm, "\t$rt, $imm32")> ; def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>; - - //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index eccc288..68a8da0 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -86,7 +86,9 @@ # CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00] # CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00] # CHECK: sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00] +# CHECK: addi $sp, $sp, -56 # encoding: [0xc8,0xff,0xbd,0x23] # CHECK: subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00] +# CHECK: addiu $sp, $sp, -40 # encoding: [0xd8,0xff,0xbd,0x27] # CHECK: neg $6, $7 # encoding: [0x22,0x30,0x07,0x00] # CHECK: negu $6, $7 # encoding: [0x23,0x30,0x07,0x00] # CHECK: move $7, $8 # encoding: [0x21,0x38,0x00,0x01] @@ -109,7 +111,9 @@ mult $3,$5 multu $3,$5 sub $9,$6,$7 + sub $sp,$sp,56 subu $4,$3,$5 + subu $sp,$sp,40 neg $6,$7 negu $6,$7 move $7,$8 |