diff options
| -rw-r--r-- | include/llvm/Target/TargetData.h | 2 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 11 | ||||
| -rw-r--r-- | lib/ExecutionEngine/Interpreter/Execution.cpp | 2 | ||||
| -rw-r--r-- | lib/ExecutionEngine/JIT/Intercept.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 2 |
5 files changed, 9 insertions, 10 deletions
diff --git a/include/llvm/Target/TargetData.h b/include/llvm/Target/TargetData.h index c06165c..60c2c32 100644 --- a/include/llvm/Target/TargetData.h +++ b/include/llvm/Target/TargetData.h @@ -112,7 +112,7 @@ public: /// @note This has to exist, because this is a pass, but it should never be /// used. TargetData() : ImmutablePass(&ID) { - llvm_report_error("ERROR: Bad TargetData ctor used. " + llvm_report_error("Bad TargetData ctor used. " "Tool did not specify a TargetData to use?"); } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index b08950d..0c410fb 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -5074,7 +5074,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { Input.ConstraintVT.isInteger()) || (OpInfo.ConstraintVT.getSizeInBits() != Input.ConstraintVT.getSizeInBits())) { - llvm_report_error("llvm: error: Unsupported asm: input constraint" + llvm_report_error("Unsupported asm: input constraint" " with a matching output constraint of incompatible" " type!"); } @@ -5179,7 +5179,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // Copy the output from the appropriate register. Find a register that // we can use. if (OpInfo.AssignedRegs.Regs.empty()) { - llvm_report_error("llvm: error: Couldn't allocate output reg for" + llvm_report_error("Couldn't allocate output reg for" " constraint '" + OpInfo.ConstraintCode + "'!"); } @@ -5233,8 +5233,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) { // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. if (OpInfo.isIndirect) { - llvm_report_error("llvm: error: " - "Don't know how to handle tied indirect " + llvm_report_error("Don't know how to handle tied indirect " "register inputs yet!"); } RegsForValue MatchedRegs; @@ -5277,7 +5276,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], hasMemory, Ops, DAG); if (Ops.empty()) { - llvm_report_error("llvm: error: Invalid operand for inline asm" + llvm_report_error("Invalid operand for inline asm" " constraint '" + OpInfo.ConstraintCode + "'!"); } @@ -5308,7 +5307,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // Copy the input into the appropriate registers. if (OpInfo.AssignedRegs.Regs.empty()) { - llvm_report_error("llvm: error: Couldn't allocate input reg for" + llvm_report_error("Couldn't allocate input reg for" " constraint '"+ OpInfo.ConstraintCode +"'!"); } diff --git a/lib/ExecutionEngine/Interpreter/Execution.cpp b/lib/ExecutionEngine/Interpreter/Execution.cpp index b351ba2..8d21d1f 100644 --- a/lib/ExecutionEngine/Interpreter/Execution.cpp +++ b/lib/ExecutionEngine/Interpreter/Execution.cpp @@ -644,7 +644,7 @@ void Interpreter::visitUnwindInst(UnwindInst &I) { } void Interpreter::visitUnreachableInst(UnreachableInst &I) { - llvm_report_error("ERROR: Program executed an 'unreachable' instruction!"); + llvm_report_error("Program executed an 'unreachable' instruction!"); } void Interpreter::visitBranchInst(BranchInst &I) { diff --git a/lib/ExecutionEngine/JIT/Intercept.cpp b/lib/ExecutionEngine/JIT/Intercept.cpp index feb13c6..0dde845 100644 --- a/lib/ExecutionEngine/JIT/Intercept.cpp +++ b/lib/ExecutionEngine/JIT/Intercept.cpp @@ -141,7 +141,7 @@ void *JIT::getPointerToNamedFunction(const std::string &Name, return RP; if (AbortOnFailure) { - llvm_report_error("ERROR: Program used external function '"+Name+ + llvm_report_error("Program used external function '"+Name+ "' which could not be resolved!"); } return 0; diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index ef7c95f..7b497a7 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -749,7 +749,7 @@ void Emitter<CodeEmitter>::emitDataProcessingInstruction( const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::BFC) { - llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported."); + llvm_report_error("ARMv6t2 JIT is not yet supported."); } // Part of binary is determined by TableGn. |