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-rw-r--r--lib/CodeGen/MachineLICM.cpp29
-rw-r--r--test/CodeGen/ARM/lsr-unfolded-offset.ll3
-rw-r--r--test/CodeGen/X86/licm-dominance.ll56
-rw-r--r--test/CodeGen/X86/licm-nested.ll2
-rw-r--r--test/CodeGen/X86/sink-hoist.ll59
-rw-r--r--test/CodeGen/X86/widen_arith-4.ll1
6 files changed, 62 insertions, 88 deletions
diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index bd25b2c..d310f25 100644
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -168,11 +168,6 @@ namespace {
///
bool IsLoopInvariantInst(MachineInstr &I);
- /// IsGuaranteedToExecute - check to make sure that the MI dominates
- /// all of the exit blocks. If it doesn't, then there is a path out of the
- /// loop which does not execute this instruction, so we can't hoist it.
- bool IsGuaranteedToExecute(MachineInstr *MI);
-
/// HasAnyPHIUse - Return true if the specified register is used by any
/// phi node.
bool HasAnyPHIUse(unsigned Reg) const;
@@ -1134,28 +1129,6 @@ bool MachineLICM::EliminateCSE(MachineInstr *MI,
return false;
}
-/// IsGuaranteedToExecute - check to make sure that the instruction dominates
-/// all of the exit blocks. If it doesn't, then there is a path out of the loop
-/// which does not execute this instruction, so we can't hoist it.
-bool MachineLICM::IsGuaranteedToExecute(MachineInstr *MI) {
- // If the instruction is in the header block for the loop (which is very
- // common), it is always guaranteed to dominate the exit blocks. Since this
- // is a common case, and can save some work, check it now.
- if (MI->getParent() == CurLoop->getHeader())
- return true;
-
- // Get the exit blocks for the current loop.
- SmallVector<MachineBasicBlock*, 8> ExitingBlocks;
- CurLoop->getExitingBlocks(ExitingBlocks);
-
- // Verify that the block dominates each of the exit blocks of the loop.
- for (unsigned i = 0, e = ExitingBlocks.size(); i != e; ++i)
- if (!DT->dominates(MI->getParent(), ExitingBlocks[i]))
- return false;
-
- return true;
-}
-
/// Hoist - When an instruction is found to use only loop invariant operands
/// that are safe to hoist, this instruction is called to do the dirty work.
///
@@ -1166,8 +1139,6 @@ bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
MI = ExtractHoistableLoad(MI);
if (!MI) return false;
}
- if (!IsGuaranteedToExecute(MI))
- return false;
// Now move the instructions to the predecessor, inserting it before any
// terminator instructions.
diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll
index bf26a96..61b25bb 100644
--- a/test/CodeGen/ARM/lsr-unfolded-offset.ll
+++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll
@@ -4,11 +4,12 @@
; register pressure and therefore spilling. There is more room for improvement
; here.
-; CHECK: sub sp, #{{40|32|28|24}}
+; CHECK: sub sp, #{{32|28|24}}
; CHECK: %for.inc
; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
+; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
; CHECK: add
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
diff --git a/test/CodeGen/X86/licm-dominance.ll b/test/CodeGen/X86/licm-dominance.ll
deleted file mode 100644
index cf3f2e8..0000000
--- a/test/CodeGen/X86/licm-dominance.ll
+++ /dev/null
@@ -1,56 +0,0 @@
-; RUN: llc < %s | FileCheck %s
-
-; MachineLICM should check dominance before hoisting instructions.
-; CHECK: xorb %cl, %cl
-; CHECK-NEXT: testb %cl, %cl
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-apple-macosx10.7.2"
-
-define void @CMSColorWorldCreateParametricData() nounwind uwtable optsize ssp {
-entry:
- br label %for.body.i
-
-for.body.i: ; preds = %entry
- br i1 undef, label %for.inc.i, label %land.lhs.true21.i
-
-land.lhs.true21.i: ; preds = %for.body.i
- br i1 undef, label %if.then26.i, label %for.inc.i
-
-if.then26.i: ; preds = %land.lhs.true21.i
- br i1 undef, label %if.else.i.i, label %if.then.i.i
-
-if.then.i.i: ; preds = %if.then26.i
- unreachable
-
-if.else.i.i: ; preds = %if.then26.i
- br i1 undef, label %lor.lhs.false.i.i, label %if.then116.i.i
-
-lor.lhs.false.i.i: ; preds = %if.else.i.i
- br i1 undef, label %lor.lhs.false104.i.i, label %if.then116.i.i
-
-lor.lhs.false104.i.i: ; preds = %lor.lhs.false.i.i
- br i1 undef, label %lor.lhs.false108.i.i, label %if.then116.i.i
-
-lor.lhs.false108.i.i: ; preds = %lor.lhs.false104.i.i
- br i1 undef, label %lor.lhs.false112.i.i, label %if.then116.i.i
-
-lor.lhs.false112.i.i: ; preds = %lor.lhs.false108.i.i
- br i1 undef, label %if.else232.i.i, label %if.then116.i.i
-
-if.then116.i.i: ; preds = %lor.lhs.false112.i.i, %lor.lhs.false108.i.i, %lor.lhs.false104.i.i, %lor.lhs.false.i.i, %if.else.i.i
- unreachable
-
-if.else232.i.i: ; preds = %lor.lhs.false112.i.i
- br label %for.inc.i
-
-for.inc.i: ; preds = %if.else232.i.i, %land.lhs.true21.i, %for.body.i
- %cmp17.i = icmp ult i64 undef, undef
- br i1 %cmp17.i, label %for.body.i, label %if.end28.i
-
-if.end28.i: ; preds = %for.inc.i, %if.then10.i, %if.then6.i
- unreachable
-
-createTransformParams.exit: ; preds = %land.lhs.true3.i, %if.then.i, %land.lhs.true.i, %entry
- ret void
-}
diff --git a/test/CodeGen/X86/licm-nested.ll b/test/CodeGen/X86/licm-nested.ll
index 901d987..b0105ac 100644
--- a/test/CodeGen/X86/licm-nested.ll
+++ b/test/CodeGen/X86/licm-nested.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep machine-licm | grep 2
+; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep machine-licm | grep 3
; MachineLICM should be able to hoist the symbolic addresses out of
; the inner loops.
diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll
index 6942b35..31f41ee 100644
--- a/test/CodeGen/X86/sink-hoist.ll
+++ b/test/CodeGen/X86/sink-hoist.ll
@@ -84,6 +84,65 @@ return:
; ret i8 %b_addr.0
; }
+; Codegen should hoist and CSE these constants.
+
+; CHECK: vv:
+; CHECK: LCPI3_0(%rip), %xmm0
+; CHECK: LCPI3_1(%rip), %xmm1
+; CHECK: LCPI3_2(%rip), %xmm2
+; CHECK: align
+; CHECK-NOT: LCPI
+; CHECK: ret
+
+@_minusZero.6007 = internal constant <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00> ; <<4 x float>*> [#uses=0]
+@twoTo23.6008 = internal constant <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06> ; <<4 x float>*> [#uses=0]
+
+define void @vv(float* %y, float* %x, i32* %n) nounwind ssp {
+entry:
+ br label %bb60
+
+bb: ; preds = %bb60
+ %0 = bitcast float* %x_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ %1 = load <4 x float>* %0, align 16 ; <<4 x float>> [#uses=4]
+ %tmp20 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp22 = and <4 x i32> %tmp20, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ; <<4 x i32>> [#uses=1]
+ %tmp23 = bitcast <4 x i32> %tmp22 to <4 x float> ; <<4 x float>> [#uses=1]
+ %tmp25 = bitcast <4 x float> %1 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp27 = and <4 x i32> %tmp25, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> ; <<4 x i32>> [#uses=2]
+ %tmp30 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %tmp23, <4 x float> <float 8.388608e+06, float 8.388608e+06, float 8.388608e+06, float 8.388608e+06>, i8 5) ; <<4 x float>> [#uses=1]
+ %tmp34 = bitcast <4 x float> %tmp30 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp36 = xor <4 x i32> %tmp34, <i32 -1, i32 -1, i32 -1, i32 -1> ; <<4 x i32>> [#uses=1]
+ %tmp37 = and <4 x i32> %tmp36, <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200> ; <<4 x i32>> [#uses=1]
+ %tmp42 = or <4 x i32> %tmp37, %tmp27 ; <<4 x i32>> [#uses=1]
+ %tmp43 = bitcast <4 x i32> %tmp42 to <4 x float> ; <<4 x float>> [#uses=2]
+ %tmp45 = fadd <4 x float> %1, %tmp43 ; <<4 x float>> [#uses=1]
+ %tmp47 = fsub <4 x float> %tmp45, %tmp43 ; <<4 x float>> [#uses=2]
+ %tmp49 = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %1, <4 x float> %tmp47, i8 1) ; <<4 x float>> [#uses=1]
+ %2 = bitcast <4 x float> %tmp49 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %3 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %2) nounwind readnone ; <<4 x float>> [#uses=1]
+ %tmp53 = fadd <4 x float> %tmp47, %3 ; <<4 x float>> [#uses=1]
+ %tmp55 = bitcast <4 x float> %tmp53 to <4 x i32> ; <<4 x i32>> [#uses=1]
+ %tmp57 = or <4 x i32> %tmp55, %tmp27 ; <<4 x i32>> [#uses=1]
+ %tmp58 = bitcast <4 x i32> %tmp57 to <4 x float> ; <<4 x float>> [#uses=1]
+ %4 = bitcast float* %y_addr.0 to <4 x float>* ; <<4 x float>*> [#uses=1]
+ store <4 x float> %tmp58, <4 x float>* %4, align 16
+ %5 = getelementptr float* %x_addr.0, i64 4 ; <float*> [#uses=1]
+ %6 = getelementptr float* %y_addr.0, i64 4 ; <float*> [#uses=1]
+ %7 = add i32 %i.0, 4 ; <i32> [#uses=1]
+ br label %bb60
+
+bb60: ; preds = %bb, %entry
+ %i.0 = phi i32 [ 0, %entry ], [ %7, %bb ] ; <i32> [#uses=2]
+ %x_addr.0 = phi float* [ %x, %entry ], [ %5, %bb ] ; <float*> [#uses=2]
+ %y_addr.0 = phi float* [ %y, %entry ], [ %6, %bb ] ; <float*> [#uses=2]
+ %8 = load i32* %n, align 4 ; <i32> [#uses=1]
+ %9 = icmp sgt i32 %8, %i.0 ; <i1> [#uses=1]
+ br i1 %9, label %bb, label %return
+
+return: ; preds = %bb60
+ ret void
+}
+
declare <4 x float> @llvm.x86.sse.cmp.ps(<4 x float>, <4 x float>, i8) nounwind readnone
declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone
diff --git a/test/CodeGen/X86/widen_arith-4.ll b/test/CodeGen/X86/widen_arith-4.ll
index b8b26e6..5931d63 100644
--- a/test/CodeGen/X86/widen_arith-4.ll
+++ b/test/CodeGen/X86/widen_arith-4.ll
@@ -1,6 +1,5 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s
; CHECK: psubw
-; CHECK-NEXT: movdqa
; CHECK-NEXT: pmullw
; Widen a v5i16 to v8i16 to do a vector sub and multiple
generated by cgit v1.1 at 2024-09-09 07:36:48 +0000