diff options
| -rw-r--r-- | lib/Target/X86/X86InstrSystem.td | 9 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrVMX.td | 28 | ||||
| -rw-r--r-- | test/MC/Disassembler/X86/simple-tests.txt | 3 | ||||
| -rw-r--r-- | test/MC/Disassembler/X86/x86-32.txt | 3 | ||||
| -rw-r--r-- | utils/TableGen/X86RecognizableInstr.cpp | 4 |
5 files changed, 31 insertions, 16 deletions
diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td index 05a5b36..b5651f3 100644 --- a/lib/Target/X86/X86InstrSystem.td +++ b/lib/Target/X86/X86InstrSystem.td @@ -465,3 +465,12 @@ let Predicates = [In64BitMode] in { def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$dst), "wrgsbase{q}\t$dst", []>, TB, XS; } + +//===----------------------------------------------------------------------===// +// INVPCID Instruction +def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), + "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8, + Requires<[In32BitMode]>; +def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), + "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8, + Requires<[In64BitMode]>; diff --git a/lib/Target/X86/X86InstrVMX.td b/lib/Target/X86/X86InstrVMX.td index 09a7a7d..74477cd 100644 --- a/lib/Target/X86/X86InstrVMX.td +++ b/lib/Target/X86/X86InstrVMX.td @@ -17,14 +17,18 @@ // 66 0F 38 80 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), - "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8; + "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8, + Requires<[In32BitMode]>; def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), - "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8; + "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8, + Requires<[In64BitMode]>; // 66 0F 38 81 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2), - "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8; + "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8, + Requires<[In32BitMode]>; def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2), - "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8; + "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8, + Requires<[In64BitMode]>; // 0F 01 C1 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB; def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), @@ -38,21 +42,21 @@ def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs), def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins), "vmptrst\t$vmcs", []>, TB; def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src), - "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB; + "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), - "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB; + "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src), - "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB; + "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In32BitMode]>; def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), - "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB; + "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In32BitMode]>; def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), - "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB; + "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), - "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB; + "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>; def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB; + "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In32BitMode]>; def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), - "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB; + "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In32BitMode]>; // 0F 01 C4 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB; def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon), diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index dc45366..b82cac6 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -309,6 +309,9 @@ # CHECK: invvpid (%rax), %rax 0x66 0x0f 0x38 0x81 0x00 +# CHECK: invpcid (%rax), %rax +0x66 0x0f 0x38 0x82 0x00 + # CHECK: nop 0x90 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 5b00769..7e02b39 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -328,6 +328,9 @@ # CHECK: invvpid (%eax), %eax 0x66 0x0f 0x38 0x81 0x00 +# CHECK: invpcid (%eax), %eax +0x66 0x0f 0x38 0x82 0x00 + # CHECK: nop 0x90 diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 617a873..6c4c584 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -257,10 +257,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, Rec->getName() == "PUSHFS64" || Rec->getName() == "PUSHGS64" || Rec->getName() == "REX64_PREFIX" || - Rec->getName().find("VMREAD64") != Name.npos || - Rec->getName().find("VMWRITE64") != Name.npos || - Rec->getName().find("INVEPT64") != Name.npos || - Rec->getName().find("INVVPID64") != Name.npos || Rec->getName().find("MOV64") != Name.npos || Rec->getName().find("PUSH64") != Name.npos || Rec->getName().find("POP64") != Name.npos; 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