diff options
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAGISel.h | 10 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 4 |
3 files changed, 11 insertions, 7 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 497040d..047da7c 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -74,7 +74,9 @@ public: /// CanBeFoldedBy - Returns true if the specific operand node N of U can be /// folded during instruction selection that starts at Root? - virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { return true;} + virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const { + return true; + } /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer /// to use for this target when scheduling the DAG. @@ -164,8 +166,10 @@ protected: SelectionDAG &DAG); // Calls to these predicates are generated by tblgen. - bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS); - bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, int64_t DesiredMaskS); + bool CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, + int64_t DesiredMaskS) const; + bool CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, + int64_t DesiredMaskS) const; private: void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 9256faa..05578fe 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -4799,7 +4799,7 @@ HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() { /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value /// specified in the .td file (e.g. 255). bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, - int64_t DesiredMaskS) { + int64_t DesiredMaskS) const { uint64_t ActualMask = RHS->getValue(); uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); @@ -4828,7 +4828,7 @@ bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS, /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value /// specified in the .td file (e.g. 255). bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS, - int64_t DesiredMaskS) { + int64_t DesiredMaskS) const { uint64_t ActualMask = RHS->getValue(); uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType()); diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 8b1690c..5eb5136 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -132,7 +132,7 @@ namespace { virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF); - virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root); + virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const; // Include the pieces autogenerated from the target description. #include "X86GenDAGISel.inc" @@ -272,7 +272,7 @@ static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse, } -bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) { +bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const { if (FastISel) return false; // If U use can somehow reach N through another path then U can't fold N or |