diff options
-rw-r--r-- | lib/CodeGen/VirtRegMap.cpp | 11 | ||||
-rw-r--r-- | test/CodeGen/X86/2008-08-06-RewriterBug.ll | 40 |
2 files changed, 48 insertions, 3 deletions
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index b9e96b1..c06ff71 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -560,8 +560,11 @@ static void InvalidateKills(MachineInstr &MI, BitVector &RegKills, if (!MO.isRegister() || !MO.isUse() || !MO.isKill()) continue; unsigned Reg = MO.getReg(); + if (TargetRegisterInfo::isVirtualRegister(Reg)) + continue; if (KillRegs) KillRegs->push_back(Reg); + assert(Reg < KillOps.size()); if (KillOps[Reg] == &MO) { RegKills.reset(Reg); KillOps[Reg] = NULL; @@ -943,9 +946,11 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, return false; continue; } - PhysReg = VRM.getPhys(VirtReg); - if (!TRI->regsOverlap(PhysReg, UnfoldPR)) - continue; + if (VRM.hasPhys(VirtReg)) { + PhysReg = VRM.getPhys(VirtReg); + if (!TRI->regsOverlap(PhysReg, UnfoldPR)) + continue; + } // Ok, we'll need to reload the value into a register which makes // it impossible to perform the store unfolding optimization later. diff --git a/test/CodeGen/X86/2008-08-06-RewriterBug.ll b/test/CodeGen/X86/2008-08-06-RewriterBug.ll new file mode 100644 index 0000000..9371c2a --- /dev/null +++ b/test/CodeGen/X86/2008-08-06-RewriterBug.ll @@ -0,0 +1,40 @@ +; RUN: llvm-as < %s | llc -march=x86 +; PR2596 + +@data = external global [400 x i64] ; <[400 x i64]*> [#uses=5] + +define void @foo(double* noalias, double* noalias) { + load i64* getelementptr ([400 x i64]* @data, i32 0, i64 200), align 4 ; <i64>:3 [#uses=1] + load i64* getelementptr ([400 x i64]* @data, i32 0, i64 199), align 4 ; <i64>:4 [#uses=1] + load i64* getelementptr ([400 x i64]* @data, i32 0, i64 198), align 4 ; <i64>:5 [#uses=2] + load i64* getelementptr ([400 x i64]* @data, i32 0, i64 197), align 4 ; <i64>:6 [#uses=1] + br i1 false, label %28, label %7 + +; <label>:7 ; preds = %2 + load double** getelementptr (double** bitcast ([400 x i64]* @data to double**), i64 180), align 8 ; <double*>:8 [#uses=1] + bitcast double* %8 to double* ; <double*>:9 [#uses=1] + ptrtoint double* %9 to i64 ; <i64>:10 [#uses=1] + mul i64 %4, %3 ; <i64>:11 [#uses=1] + add i64 0, %11 ; <i64>:12 [#uses=1] + shl i64 %12, 3 ; <i64>:13 [#uses=1] + sub i64 %10, %13 ; <i64>:14 [#uses=1] + add i64 %5, 0 ; <i64>:15 [#uses=1] + shl i64 %15, 3 ; <i64>:16 [#uses=1] + bitcast i64 %16 to i64 ; <i64>:17 [#uses=1] + mul i64 %6, %5 ; <i64>:18 [#uses=1] + add i64 0, %18 ; <i64>:19 [#uses=1] + shl i64 %19, 3 ; <i64>:20 [#uses=1] + sub i64 %17, %20 ; <i64>:21 [#uses=1] + add i64 0, %21 ; <i64>:22 [#uses=1] + add i64 0, %14 ; <i64>:23 [#uses=1] + br label %24 + +; <label>:24 ; preds = %24, %7 + phi i64 [ 0, %24 ], [ %22, %7 ] ; <i64>:25 [#uses=1] + phi i64 [ 0, %24 ], [ %23, %7 ] ; <i64>:26 [#uses=0] + add i64 %25, 24 ; <i64>:27 [#uses=0] + br label %24 + +; <label>:28 ; preds = %2 + unreachable +} |