diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 14 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 41 | ||||
| -rw-r--r-- | test/MC/PowerPC/ppc64-encoding.s | 38 |
3 files changed, 84 insertions, 9 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index a244058..b316fa6 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -145,6 +145,20 @@ class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, let Inst{31} = lk; } +class BForm_3<bits<6> opcode, bit aa, bit lk, + dag OOL, dag IOL, string asmstr> + : I<opcode, OOL, IOL, asmstr, BrB> { + bits<5> BO; + bits<5> BI; + bits<14> BD; + + let Inst{6-10} = BO; + let Inst{11-15} = BI; + let Inst{16-29} = BD; + let Inst{30} = aa; + let Inst{31} = lk; +} + // 1.7.3 SC-Form class SCForm<bits<6> opcode, bits<1> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index dcea65c..7934da9 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -2229,6 +2229,47 @@ def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; +// These generic branch instruction forms are used for the assembler parser only. +// Defs and Uses are conservative, since we don't know the BO value. +let PPC970_Unit = 7 in { + let Defs = [CTR], Uses = [CTR, RM] in { + def gBC : BForm_3<16, 0, 0, (outs), + (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), + "bc $bo, $bi, $dst">; + def gBCA : BForm_3<16, 1, 0, (outs), + (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), + "bca $bo, $bi, $dst">; + } + let Defs = [LR, CTR], Uses = [CTR, RM] in { + def gBCL : BForm_3<16, 0, 1, (outs), + (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), + "bcl $bo, $bi, $dst">; + def gBCLA : BForm_3<16, 1, 1, (outs), + (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), + "bcla $bo, $bi, $dst">; + } + let Defs = [CTR], Uses = [CTR, LR, RM] in + def gBCLR : XLForm_2<19, 16, 0, (outs), + (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), + "bclr $bo, $bi, $bh", BrB, []>; + let Defs = [LR, CTR], Uses = [CTR, LR, RM] in + def gBCLRL : XLForm_2<19, 16, 1, (outs), + (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), + "bclrl $bo, $bi, $bh", BrB, []>; + let Defs = [CTR], Uses = [CTR, LR, RM] in + def gBCCTR : XLForm_2<19, 528, 0, (outs), + (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), + "bcctr $bo, $bi, $bh", BrB, []>; + let Defs = [LR, CTR], Uses = [CTR, LR, RM] in + def gBCCTRL : XLForm_2<19, 528, 1, (outs), + (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), + "bcctrl $bo, $bi, $bh", BrB, []>; +} +def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; +def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; +def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; +def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; + multiclass BranchExtendedMnemonic<string name, int bibo> { def : InstAlias<"b"#name#" $cc, $dst", (BCC bibo, crrc:$cc, condbrtarget:$dst)>; diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s index cf6f784..377000f 100644 --- a/test/MC/PowerPC/ppc64-encoding.s +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -18,15 +18,35 @@ # CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24abs bla target -# FIXME: bc 4, 10, target -# FIXME: bca 4, 10, target -# FIXME: bcl 4, 10, target -# FIXME: bcla 4, 10, target - -# FIXME: bclr 4, 10, 3 -# FIXME: bclrl 4, 10, 3 -# FIXME: bcctr 4, 10, 3 -# FIXME: bcctrl 4, 10, 3 +# CHECK: bc 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bc 4, 10, target +# CHECK: bca 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA10] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bca 4, 10, target +# CHECK: bcl 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA01] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bcl 4, 10, target +# CHECK: bcla 4, 10, target # encoding: [0x40,0x8a,A,0bAAAAAA11] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14abs + bcla 4, 10, target + +# CHECK: bclr 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x20] + bclr 4, 10, 3 +# CHECK: bclr 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x20] + bclr 4, 10 +# CHECK: bclrl 4, 10, 3 # encoding: [0x4c,0x8a,0x18,0x21] + bclrl 4, 10, 3 +# CHECK: bclrl 4, 10, 0 # encoding: [0x4c,0x8a,0x00,0x21] + bclrl 4, 10 +# CHECK: bcctr 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x20] + bcctr 4, 10, 3 +# CHECK: bcctr 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x20] + bcctr 4, 10 +# CHECK: bcctrl 4, 10, 3 # encoding: [0x4c,0x8a,0x1c,0x21] + bcctrl 4, 10, 3 +# CHECK: bcctrl 4, 10, 0 # encoding: [0x4c,0x8a,0x04,0x21] + bcctrl 4, 10 # Condition register instructions |