diff options
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index b4c795b..04ef958 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -138,7 +138,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); - if (Subtarget->isSingleFloat()) + if (Subtarget->isSingleFloat()) setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); if (!Subtarget->hasSEInReg()) { diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 312cc0b..8e05ac5 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -339,3 +339,8 @@ def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1A (TRUNC_W_AS32 AFGR32:$src))>; def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>; def : Pat<(i32 (bitconvert AFGR32:$src)), (MFC1A AFGR32:$src)>; + +def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>, + Requires<[IsSingleFloat]>; +def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1A CPURegs:$src)>, + Requires<[In32BitMode]>; |